An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic

2004 ◽  
Author(s):  
D.J. Allred ◽  
W. Huang ◽  
V. Krishnan ◽  
Heejong Yoo ◽  
D.V. Anderson
Keyword(s):  
High Throughput ◽  
Adaptive Filter ◽  
Fpga Implementation ◽  
Distributed Arithmetic

scholarly journals Low Power High Throughput Memory Less Adaptive Filter using Distributed Arithmetic

2019 ◽  
Vol 8 (10) ◽  
pp. 3381-3384
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Throughput ◽  
Adaptive Filter ◽  
Inner Product ◽  
Filter Coefficient ◽  
Distributed Arithmetic ◽  
Area Efficient

This paper briefs an area efficient, low power and high throughput LMS adaptive filter using Distributed Arithmetic architecture. The throughput is increased because of parallel updating of filter coefficient and computing the inner product simultaneously. Here we have proposed memory-less design of distributed arithmetic (MLDA) unit. The proposed design uses 2:1 multiplexer’s architecture to replace LUT of the conventional DA to reduce the overall area of the filter. Enhanced compressor adder is used for accumulation of the partial products, which further helps to reduce the area. Parallel updating of the generation and accumulation enhance the throughput of the design. The proposed architecture requires more than half area that required for the existing LUT based inner product block. The proposed design is implemented in synopsis design compiler and the result shows that the area decreased by 52.7% and also the MUX based DA for the Adaptive filter causes 69.25% less power consumption for filter tap N=16, 32 and 64. Proposed design provides 36.50% less Area Delay Product (ADP).

ASIC Implementation of Area-Efficient, High-Throughput 2-D IIR Filter Using Distributed Arithmetic

2017 ◽  
Vol 37 (7) ◽  
pp. 2934-2957 ◽  
Author(s):  
Prashant Kumar ◽  
Prabhat Chandra Shrivastava ◽  
Manish Tiwari ◽  
Amit Dhawan
Keyword(s):  
High Throughput ◽  
Distributed Arithmetic ◽  
Iir Filter ◽  
Area Efficient
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