scholarly journals Low Power High Throughput Memory Less Adaptive Filter using Distributed Arithmetic

2019 ◽  
Vol 8 (10) ◽  
pp. 3381-3384
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Throughput ◽  
Adaptive Filter ◽  
Inner Product ◽  
Filter Coefficient ◽  
Distributed Arithmetic ◽  
Area Efficient

This paper briefs an area efficient, low power and high throughput LMS adaptive filter using Distributed Arithmetic architecture. The throughput is increased because of parallel updating of filter coefficient and computing the inner product simultaneously. Here we have proposed memory-less design of distributed arithmetic (MLDA) unit. The proposed design uses 2:1 multiplexer’s architecture to replace LUT of the conventional DA to reduce the overall area of the filter. Enhanced compressor adder is used for accumulation of the partial products, which further helps to reduce the area. Parallel updating of the generation and accumulation enhance the throughput of the design. The proposed architecture requires more than half area that required for the existing LUT based inner product block. The proposed design is implemented in synopsis design compiler and the result shows that the area decreased by 52.7% and also the MUX based DA for the Adaptive filter causes 69.25% less power consumption for filter tap N=16, 32 and 64. Proposed design provides 36.50% less Area Delay Product (ADP).

ASIC Implementation of Area-Efficient, High-Throughput 2-D IIR Filter Using Distributed Arithmetic

2017 ◽  
Vol 37 (7) ◽  
pp. 2934-2957 ◽  
Author(s):  
Prashant Kumar ◽  
Prabhat Chandra Shrivastava ◽  
Manish Tiwari ◽  
Amit Dhawan
Keyword(s):  
High Throughput ◽  
Distributed Arithmetic ◽  
Iir Filter ◽  
Area Efficient

Low power area efficient adaptive FIR filter for hearing aids using distributed arithmetic architecture

2020 ◽  
Vol 23 (2) ◽  
pp. 287-296 ◽  
Author(s):  
P. V. Praveen Sundar ◽  
D. Ranjith ◽  
T. Karthikeyan ◽  
V. Vinoth Kumar ◽  
Balajee Jeyakumar
Keyword(s):  
Low Power ◽  
Hearing Aids ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Adaptive Fir ◽  
Area Efficient

A Low-Power and Area-Efficient 64-Bit Digital Comparator

2016 ◽  
Vol 25 (12) ◽  
pp. 1650148 ◽  
Author(s):  
N. V. Vijaya Krishna Boppana ◽  
Saiyu Ren
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Resource Sharing ◽  
Portable Devices ◽  
Worst Case ◽  
Lower Power ◽  
Digital Comparator ◽  
Area Efficient

A new low-power and area-efficient radix-4 tree-based 64-bit digital comparator is presented in this paper. The proposed design with 64 XOR-XNOR (XE) blocks is custom implemented in 90[Formula: see text]nm 1.2[Formula: see text]V multi-threshold technology using Cadence-Virtuoso layout editor. The 64 bit comparator has an area of 1009[Formula: see text][Formula: see text], a worst case delay of 858[Formula: see text]ps, and a power consumption of 898[Formula: see text]uW at 1[Formula: see text]G bit/s. The two features, lower power consumption and smaller area compared to other published comparators, make the proposed design most suitable for low-power portable devices. Resource sharing is an important feature for the proposed design. The 64 XE blocks occupy approximately 60% (600[Formula: see text][Formula: see text]) of the total comparator area and contributes 54% (484[Formula: see text][Formula: see text]W) of the total worst power consumption. The 64 XE blocks can also be used to design XE based 64-bit adders, encryption devices, etc.

scholarly journals Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 256
Author(s):  
Youngbae Kim ◽  
Shreyash Patel ◽  
Heekyung Kim ◽  
Nandakishor Yadav ◽  
Kyuwon Ken Choi
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
Low Power ◽  
High Throughput ◽  
Autonomous Vehicles ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
Electrical Performance ◽  
Large Area ◽  
Ultra Low Power

Power consumption and data processing speed of integrated circuits (ICs) is an increasing concern in many emerging Artificial Intelligence (AI) applications, such as autonomous vehicles and Internet of Things (IoT). Existing state-of-the-art SRAM architectures for AI computing are highly accurate and can provide high throughput. However, these SRAMs have problems that they consume high power and occupy a large area to accommodate complex AI models. A carbon nanotube field-effect transistors (CNFET) device has been reported as a potential candidates for AI devices requiring ultra-low power and high-throughput due to their satisfactory carrier mobility and symmetrical, good subthreshold electrical performance. Based on the CNFET and FinFET device’s electrical performance, we propose novel ultra-low power and high-throughput 8T SRAMs to circumvent the power and the throughput issues in Artificial Intelligent (AI) computation for autonomous vehicles. We propose two types of novel 8T SRAMs, P-Latch N-Access (PLNA) 8T SRAM structure and single-ended (SE) 8T SRAM structure, and compare the performance with existing state-of-the-art 8T SRAM architectures in terms of power consumption and speed. In the SRAM circuits of the FinFET and CNFET, higher tube and fin numbers lead to higher operating speed. However, the large number of tubes and fins can lead to larger area and more power consumption. Therefore, we optimize the area by reducing the number of tubes and fins without compromising the memory circuit speed and power. Most importantly, the decoupled reading and writing of our new SRAMs cell offers better low-power operation due to the stacking of device in the reading part, as well as achieving better readability and writability, while offering read Static Noise Margin (SNM) free because of isolated reading path, writing path, and greater pull up ratio. In addition, the proposed 8T SRAMs show even better performance in delay and power when we combine them with the collaborated voltage sense amplifier and independent read component. The proposed PLNA 8T SRAM can save 96%, while the proposed SE 8T SRAM saves around 99% in writing power consumption compared with the existing state-of-the-art 8T SRAM in FinFET model, as well as 99% for writing operation in CNFET model.

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