An efficient FIR filter based on hardware sharing architecture using CSD coefficient grouping for wireless application

FIR filter is an essential part of digital signal processing that is extensively used in many areas such as wireless application and digital processing system. An efficient recursive filter is always required for real-time applications such as 5G network, smart robots and Internet of Things etc. The design of FIR filter is inherently stable and has a linear phase characteristic but its implementation often involves complexity and a large filter length to achieve specific design requirements. In this paper, the complexity of FIR filter is reduced by eliminating the repeated subexpression in a canonic sign digit(CSD)number system based filter operation. A new grouping method has been proposed for the CSD number system-based filter coefficient to minimize the number of unpaired nonzero bits in the filter coefficient. The statistical analysis of the proposed grouping method is performed and compared with other existing schemes. The number of unpaired nonzero bits in the proposed grouping scheme is reduced by an average of 24.11% as compared to other existing schemes. Further, an efficient FIR filter with hardware sharing architecture is designed and implemented to achieve a 14.65% reduction in average power consumption and the average operation speed is increased by 10.1% in comparison to the other existing filter structures.

A Low-Cost Complexity Intra Prediction Hardware Architecture for HEVC Decoder

High Efficiency Video Coding (HEVC) adopts new techniques to reduce bit-rate by 50% over a previous video compression standard. The number of intra prediction modes in HEVC is 35 modes and increased compared with the compression. Therefore, hardware architecture with common equation and a fast filter coefficient generation algorithm is proposed for low complexity intra prediction hardware. The proposed architecture performs a smoothing filter, interpolation filter, generation of predicted pixels with only Common Operation Unit (COU). Various equations in intra prediction for smoothing filter of reference samples, calculating the average of the reference samples, generating predicted pixels and filtering predicted pixels is modified to one common equation. The common operation unit using a common equation in intra prediction hardware architecture reduces hardware area and the number of computational operators to perform various equations. COU uses 2 multipliers, 9 adders, 3 shifters and generates 1 predicted sample in planar mode and 2 predicted samples in the other mode. Also, COU generates 2 filtered reference samples in filtering operation of reference samples and the average of 4x4 PU in DC mode. The fast filter coefficient generation algorithm reduces processing time by using only Look-Up Table (LUT) and adders, instead of multiplying operation and the number of computational operators. The number of gates of the architecture is 45.6k. The number of gates in the proposed intra prediction hardware is 36.7% less than previous architecture.

Physical Experiment and Modeling of the Transport and Deposition of Polydisperse Particles in Stormwater: Effects of a Depth-Dependent Initial Filter Coefficient

The artificial recharge of stormwater is an effective approach for replenishing aquifer and reduce urban waterlogging, but prone to clogging by suspended particles (SP) that are highly heterogeneously sized. In this paper, the transport and deposition of SP in a sand column were investigated under a constant flow condition, for five stormwater concentrations. A depth-dependent initial filter coefficient is incorporated into the conventional filtration model. This modified model considers the heterogeneity of the particle population by lumping the capture of heterogeneous SP into a capture probability. The good agreement between the results of the modified model and the experimental results of measured outlet concentration and average specific deposit validated the modified model. The experiment data and the simulation results both indicate that the highly hyper-exponential retention profiles are caused by non-uniform deposition of heterogeneous SP; and, the conventional model was found to homogenize the spatial distribution of SP retention and overestimate retention of the porous medium. Local and overall permeability reductions were assessed by an empirical relationship and the Kozeny-Carman model, respectively. It is shown that consideration of polydisperse suspended particles is of primary importance. This study highlights the effects of polydisperse particles on SP deposition in a saturated porous medium.

Low Power High Throughput Memory Less Adaptive Filter using Distributed Arithmetic

This paper briefs an area efficient, low power and high throughput LMS adaptive filter using Distributed Arithmetic architecture. The throughput is increased because of parallel updating of filter coefficient and computing the inner product simultaneously. Here we have proposed memory-less design of distributed arithmetic (MLDA) unit. The proposed design uses 2:1 multiplexer’s architecture to replace LUT of the conventional DA to reduce the overall area of the filter. Enhanced compressor adder is used for accumulation of the partial products, which further helps to reduce the area. Parallel updating of the generation and accumulation enhance the throughput of the design. The proposed architecture requires more than half area that required for the existing LUT based inner product block. The proposed design is implemented in synopsis design compiler and the result shows that the area decreased by 52.7% and also the MUX based DA for the Adaptive filter causes 69.25% less power consumption for filter tap N=16, 32 and 64. Proposed design provides 36.50% less Area Delay Product (ADP).