In this paper, multifunction residue number system (RNS) modulo (2n ± 1) multipliers are proposed. By adopting common circuits for summing up the partial products with extra controls, our proposed multipliers could perform both modulo (2n + 1) and (2n - 1) multiplications. The levels for summation of partial products are n + 1, which are same as the conventional modulo multipliers which with only one kind of modulo multiplications. The proposed multifunction modulo (2n ± 1) multipliers can save at least about 42.5% area under the same delay constraints and above 65.8% Area × Delay Product (ADP) compared with the one composed of modulo (2n + 1) and modulo (2n - 1) multiplication operations. Our proposed multipliers could be applied to ease the tremendous computation overload in the real-time processing applications.
An FPGA implementation of redundant residue number system for low-cost fast speed fault-tolerant computations