A systolic approach to multistage interconnection network design

2003 ◽  
Author(s):  
C.-H. Chen ◽  
L.N. Bhuyan
Keyword(s):  
Network Design ◽  
Interconnection Network ◽  
Multistage Interconnection Network

Butterfly interconnection network: design of multiplier, flip-flop, and shift register

1994 ◽  
Vol 33 (8) ◽  
pp. 1457 ◽  
Author(s):  
Khan M. Iftekharuddin ◽  
Mohammad A. Karim
Keyword(s):  
Network Design ◽  
Interconnection Network ◽  
Shift Register ◽  
Flip Flop

scholarly journals Design and Implementation of Rearrangable Non-Blocking Switching Network in VLSI

2019 ◽  
Vol 8 (2S11) ◽  
pp. 2858-2863
Keyword(s):  
Interconnection Network ◽  
The Other ◽  
Switching Network ◽  
Low Latency ◽  
Multistage Interconnection Network ◽  
Design And Implementation ◽  
Benes Network ◽  
Benes Networks

The main goal of this article is to implement an effective Non-Blocking Benes switching Network. Benes Switching Network is designed with the uncomplicated switch modules & it’s have so many advantages, small latency, less traffic and it’s required number of switch modules. Clos and Benes networks are play a key role in the class of multistage interconnection network because of their extensibility and mortality. Benes network provides a low latency when compare with the other networks. 8x8 Benes non blocking switching network is designed and synthesized with the using of Xilinx tool 12.1.

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