An improved graph-based FPGA technology mapping algorithm for delay optimization

Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors ◽

10.1109/iccd.1992.276239 ◽

2003 ◽

Author(s):

J. Cong ◽

Y. Ding ◽

A.B. Kahng ◽

P. Trajmar ◽

K.-C. Chen

Keyword(s):

Technology Mapping ◽

Mapping Algorithm ◽

Delay Optimization

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An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1992.279398 ◽

1992 ◽

Author(s):

Cong ◽

Ding

Keyword(s):

Lookup Table ◽

Technology Mapping ◽

Mapping Algorithm ◽

Delay Optimization ◽

Optimal Technology

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An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs

The Best of ICCAD ◽

10.1007/978-1-4615-0292-0_19 ◽

2003 ◽

pp. 235-248

Author(s):

Jason Cong ◽

Yuzheng Ding

Keyword(s):

Lookup Table ◽

Technology Mapping ◽

Mapping Algorithm ◽

Delay Optimization ◽

Optimal Technology

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FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.273754 ◽

1994 ◽

Vol 13 (1) ◽

pp. 1-12 ◽

Author(s):

J. Cong ◽

Yuzheng Ding

Keyword(s):

Lookup Table ◽

Technology Mapping ◽

Mapping Algorithm ◽

Delay Optimization ◽

Optimal Technology

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A new strategy of performance-directed technology mapping algorithm for LUT-based FPGAs

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96 ◽

10.1109/iscas.1996.542151 ◽

2002 ◽

Author(s):

K.N. Chen ◽

T.S. Wang ◽

Y.T. Lai

Keyword(s):

Technology Mapping ◽

Mapping Algorithm ◽

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MemMap-pd: performance driven technology mapping algorithm for FPGAs with embedded memory arrays

18th International Parallel and Distributed Processing Symposium, 2004. Proceedings. ◽

10.1109/ipdps.2004.1303140 ◽

2004 ◽

Author(s):

A.M. Kumar ◽

B. Jayaram ◽

R. Manimegalai ◽

V. Kamakoti

Keyword(s):

Technology Mapping ◽

Embedded Memory ◽

Mapping Algorithm ◽

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A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm Targeting Area Minimization

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) ◽

10.1109/iccad45719.2019.8942053 ◽

2019 ◽

Author(s):

Ghasem Pasandi ◽

Massoud Pedram

Keyword(s):

Dynamic Programming ◽

Technology Mapping ◽

Mapping Algorithm ◽

Area Minimization

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An efficient technology mapping algorithm targeting routing congestion under delay constraints

Proceedings of the 2005 international symposium on physical design - ISPD '05 ◽

10.1145/1055137.1055166 ◽

2005 ◽

Author(s):

Rupesh S. Shelar ◽

Prashant Saxena ◽

Xinning Wang ◽

Sachin S. Sapatnekar

Keyword(s):

Technology Mapping ◽

Efficient Technology ◽

Mapping Algorithm ◽

Delay Constraints ◽

Routing Congestion

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A new retiming-based technology mapping algorithm for LUT-based FPGAs

Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays - FPGA '98 ◽

10.1145/275107.275118 ◽

1998 ◽

Author(s):

Peichen Pan ◽

Chih-Chang Lin

Keyword(s):

Technology Mapping ◽

Mapping Algorithm

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Technology mapping algorithm for heterogeneous field programmable gate arrays

IEE Proceedings - Computers and Digital Techniques ◽

10.1049/ip-cdt:20020748 ◽

2002 ◽

Vol 149 (6) ◽

pp. 249 ◽

Author(s):

Y.-T. Lai ◽

C.-C. Kao

Keyword(s):

Field Programmable Gate Arrays ◽

Technology Mapping ◽

Mapping Algorithm ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

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Technology mapping algorithm targeting routing congestion under delay constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2006.870078 ◽

2006 ◽

Vol 25 (4) ◽

pp. 625-636 ◽

Author(s):

R.S. Shelar ◽

P. Saxena ◽

S.S. Sapatnekar

Keyword(s):

Technology Mapping ◽

Mapping Algorithm ◽

Delay Constraints ◽

Routing Congestion

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