Hardware Software Co-design based CPU-FPGA Architecture: Overview and Evaluation

2021 ◽  
Author(s):  
Said Agharass ◽  
Mostafa Laaboubi ◽  
Amine Saddik ◽  
Rachid Latif
Keyword(s):  
Fpga Architecture

A new FPGA architecture suitable for DSP applications

2011 ◽  
Vol 32 (5) ◽  
pp. 055012
Author(s):  
Liyun Wang ◽  
Jinmei Lai ◽  
Jiarong Tong ◽  
Pushan Tang ◽  
Xing Chen ◽  
...  
Keyword(s):  
Fpga Architecture ◽  
Dsp Applications

scholarly journals Three Dimensional FPGA Architecture with Fewer TSVs

2018 ◽  
Vol E101.D (2) ◽  
pp. 278-287 ◽  
Author(s):  
Motoki AMAGASAKI ◽  
Masato IKEBE ◽  
Qian ZHAO ◽  
Masahiro IIDA ◽  
Toshinori SUEYOSHI
Keyword(s):  
Three Dimensional ◽  
Fpga Architecture

IMPROVED TIME-MULTIPLEXED FPGA ARCHITECTURE AND ALGORITHM FOR MINIMIZING COMMUNICATION COST DESIGNS

2013 ◽  
Vol 22 (05) ◽  
pp. 1350033
Author(s):  
CHI-CHOU KAO ◽  
YEN-TAI LAI
Keyword(s):  
Greedy Algorithm ◽  
Sequential Circuits ◽  
Precedence Constraints ◽  
Communication Cost ◽  
Experimental Results ◽  
Time Sharing ◽  
Fpga Architecture ◽  
The Given

The Time-Multiplexed FPGA (TMFPGA) architecture can improve dramatically logic utilization by time-sharing logic but it needs a large amount of registers among sub-circuits for partitioning the given sequential circuits. In this paper, we propose an improved TMFPGA architecture to simplify the precedence constraints so that the number of the registers among sub-circuits can be reduced for sequential circuits partitioning. To demonstrate the practicability of the architecture, we also present a greedy algorithm to minimize the maximum number of the registers. Experimental results demonstrate the effectives of the algorithm.

A high performance, high density sea of modules FPGA architecture

2002 ◽  
Author(s):  
K. El-Ayat ◽  
S. Kaptanoglu ◽  
R. Chan ◽  
J. Lien ◽  
W. Plants ◽  
...  
Keyword(s):  
High Performance ◽  
High Density ◽  
Fpga Architecture
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