IMPROVED TIME-MULTIPLEXED FPGA ARCHITECTURE AND ALGORITHM FOR MINIMIZING COMMUNICATION COST DESIGNS
2013 ◽
Vol 22
(05)
◽
pp. 1350033
Keyword(s):
The Time-Multiplexed FPGA (TMFPGA) architecture can improve dramatically logic utilization by time-sharing logic but it needs a large amount of registers among sub-circuits for partitioning the given sequential circuits. In this paper, we propose an improved TMFPGA architecture to simplify the precedence constraints so that the number of the registers among sub-circuits can be reduced for sequential circuits partitioning. To demonstrate the practicability of the architecture, we also present a greedy algorithm to minimize the maximum number of the registers. Experimental results demonstrate the effectives of the algorithm.
2011 ◽
Vol 418-420
◽
pp. 1307-1311
2019 ◽
Vol 33
◽
pp. 5533-5540
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Keyword(s):
2009 ◽
pp. 110-135
Keyword(s):
2013 ◽
Vol 347-350
◽
pp. 3797-3803
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Keyword(s):
2020 ◽
Vol 34
(04)
◽
pp. 4158-4165
Keyword(s):
2003 ◽
Vol 1
(1)
◽
pp. 71-80
◽
Keyword(s):
2019 ◽
Vol 33
◽
pp. 4031-4038
Keyword(s):
2010 ◽
Vol 24
(04)
◽
pp. 557-579
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