Research on EMC optimization of high speed PCB design

Author(s):  
Xi Chen ◽  
Shuguo Xie ◽  
Mingmin Zhao ◽  
Chengbin Fu
Keyword(s):  
2013 ◽  
Vol 662 ◽  
pp. 846-850
Author(s):  
Jiang Hong ◽  
Zhi Wei Tang ◽  
Long Hu Chen

With the increase of integrated circuit switch rate and PCB density, signal integrity has become one of the problems must be concerned in high-speed PCB design. How to fully consider EMC (Electromagnetic compatibility) and take effective measures has been a key factor of a system design. Based on the consideration of EMC, the author put forward some aspects in designing high-speed PCB. The optimized PCB design rules have steady and credible performance, the development period is shortened and the cost is reduced. The conclusions drawn from the dissertation are helpful to the design of high-speed PCB.


1999 ◽  
Vol 11 (2) ◽  
pp. 104-111
Author(s):  
Toshifumi Honda ◽  
◽  
Hisae Yamamura ◽  
Mineo Nomoto ◽  
Takanori Ninomiya ◽  
...  

Automated visual solder inspection was studied for different printed circuit boards (PCBs) based on 3-D-image analysis. The optical 3-D scanner accurately detects height of a solder joint from differently focused images of a laser spot. Emitted laser light on the solder joint is detected simultaneously by plural sensors whose focal points are set at different height to realize high-speed height acquisition without secondary-reflection problems caused by the specular surface of the solder joint. An inspection algorithm was designed to recognize a solder joint using detected height and the intensity image so that different shapes of solder fillet do not affect inspection performance. A solder joint is classified based on extracted 3-D features of its fillet shape and 3-D location of the lead from its pad. Inspection parameters are automatically generated with inspection parameter autogeneration using electronic component and PCB design data. Evaluation showed the system gave 100% defect detection and very few false alarms (0.13%) using autogenerated inspection parameters. Results show the technique to be promising in actual production lines for different PCBs.


2004 ◽  
Vol 23 (2) ◽  
pp. 24-32 ◽  
Author(s):  
M.S. Sharawi
Keyword(s):  

2014 ◽  
Vol 670-671 ◽  
pp. 1447-1453
Author(s):  
Bao Po Wang ◽  
Jin Song Du ◽  
Xing Tian ◽  
Xin Bi

For the requirements of different bus signals from high speed PCB with DDR3 components based on fly-by topology structure, coping strategies have been proposed respectively. For the address or command bus, a leveling-free strategy has been proposed. It shows that the phase difference can be nearly zero through reasonable constraints on PCB design. The strategy was applied to the clock bus and achieved good performance, combining with the rules of signal integrity. For the data bus, the timing sequence on source synchronous has been analyzed and the time margin was calculated. The reasonability of the design was verified through the simulation result with Cadence.


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