Some Noteworthy Aspects in Designing High-Speed PCB

2013 ◽  
Vol 662 ◽  
pp. 846-850
Author(s):  
Jiang Hong ◽  
Zhi Wei Tang ◽  
Long Hu Chen
Keyword(s):  
System Design ◽  
Integrated Circuit ◽  
High Speed ◽  
Electromagnetic Compatibility ◽  
Signal Integrity ◽  
Design Rules ◽  
Pcb Design ◽  
Key Factor ◽  
Switch Rate ◽  
The Cost

With the increase of integrated circuit switch rate and PCB density, signal integrity has become one of the problems must be concerned in high-speed PCB design. How to fully consider EMC (Electromagnetic compatibility) and take effective measures has been a key factor of a system design. Based on the consideration of EMC, the author put forward some aspects in designing high-speed PCB. The optimized PCB design rules have steady and credible performance, the development period is shortened and the cost is reduced. The conclusions drawn from the dissertation are helpful to the design of high-speed PCB.

Signal Integrity Analysis of High-Speed Signal Connector USB3.0

2013 ◽  
Vol 760-762 ◽  
pp. 320-324
Author(s):  
Shi Lei Zhou ◽  
Ya Lin Guan ◽  
Xin Kun Tang
Keyword(s):  
Transmission Lines ◽  
High Speed ◽  
Signal Integrity ◽  
Signal Transmission ◽  
Simulation Software ◽  
Key Factor ◽  
Transmission Quality ◽  
Integrity Analysis ◽  
Relationship Of ◽  
The Relationship

High-speed signal connector has become a key factor of the signal transmission quality in telecommunications and data communications system. Signal integrity of connector is an inevitable problem. This paper based on the theory of differential transmission lines and Multimode S-Parameters, analyzed the USB3.0 connector signal integrity. And use 3D simulation software CST to build model and analyze the relationship of signal integrity and connectors geometry.

Interference and Electromagnetic Compatibility Challenges in 5G Wireless Network Deployments

2017 ◽  
Vol 5 (3) ◽  
pp. 612
Author(s):  
Idrissa Abubakar ◽  
Jafri Din ◽  
Manhal Alhilali ◽  
Hong Yin Lam
Keyword(s):  
Wireless Network ◽  
Electromagnetic Interference ◽  
High Speed ◽  
Electromagnetic Compatibility ◽  
Signal Integrity ◽  
Energy Coupling ◽  
Mri Scan ◽  
Power Bus ◽  
Electromagnetic Devices ◽  
High Speed Data

<p>5G wireless network technology is going operate within the environment of other electrical, electronic and electromagnetic devices, components and systems, with capability of high speed data connectivity acting as network transceiver stations with Massive MIMO for Internet of Things (IoT). Considering the level of interoperability, electromagnetic Interference and electromagnetic compatibility to avoid electromagnetic pulse effects (EMP) which is capable of not only causing network malfunctions but total devices and equipments failure in mission critical operations, like hospital MRI scan machines, security profiling and data handling or even personal healthcare devices like heart pacemaker. Electromagnetic energy coupling in PCB due to: radiation, reflection and Crosstalk generates reliability challenges affecting Signal Integrity between traces of multilayer boards stalks, power bus and packaging creating Electromagnetic interference (EMI) in PCB leading false clock response to system failure. Above were considered very essential when deploying 5G wireless network facility as presented in this paper. </p>

Automatic Feature Recognition for Data Interoperability Issues in High-Speed Electronics System Design

2008 ◽  
Author(s):  
Xiaolin Chen ◽  
Hui Zhang ◽  
Will Miller
Keyword(s):  
System Design ◽  
Design Process ◽  
High Speed ◽  
High Performance ◽  
Feature Recognition ◽  
Circuit Simulation ◽  
Signal Integrity ◽  
Electronic Systems ◽  
Design Data ◽  
Automatic Feature Recognition

Technology trends toward higher speed and density devices have pushed high performance electronic system design to its limits. With fine miniaturization of very-large-scale integrated (VLSI) circuits and rapid increase in the working frequency of system-on-a-chip (SoC), the signal integrity has become a major concern. As the operating frequencies enter the gigahertz range, signal integrity issues such as cross talk, power-ground-plane voltage bounce, and substrate losses can no longer be neglected. In order to design high-performance electronic systems with fast time-to-market, it is often needed to analyze whole or part of the system at one fundamentally deeper level of physics. It has begun to be recognized that electromagnetic (EM) field analysis needs to be rigorously included as an addition to traditional circuit simulation. A common problem in this practice is the lack of efficient tools that enable engineers to easily transfer circuit board design data into EM solvers. To partially solve this problem, ACIS SAT has been introduced as a standard data exchange format and been adopted by many software vendors for data import and export. However, efficient data transfer remains a problem as the geometry created in the design package becomes static and no longer feature-based once imported into the simulation package. In this paper, automatic feature recognition algorithms are implemented to help extract features and parameters from the imported static model in SAT format. Case studies will be provided for some representative high speed electronics designs. This work is supported by Research & Technology Development Grant Program of Washington Technology Center with a goal to achieve improved design process for high-speed electronic systems. The developed tool has a potential to speed up the current design process by eliminating laborious manual preparation of design data for EM simulation and allow what-if analysis to be automated to highlight likely signal integrity issues.

Simulation and Analysis of DDR3 Bus Based on Fly-By Topology with Cadence

2014 ◽  
Vol 670-671 ◽  
pp. 1447-1453
Author(s):  
Bao Po Wang ◽  
Jin Song Du ◽  
Xing Tian ◽  
Xin Bi
Keyword(s):  
Coping Strategies ◽  
Phase Difference ◽  
High Speed ◽  
Signal Integrity ◽  
Topology Structure ◽  
Pcb Design ◽  
Data Bus

For the requirements of different bus signals from high speed PCB with DDR3 components based on fly-by topology structure, coping strategies have been proposed respectively. For the address or command bus, a leveling-free strategy has been proposed. It shows that the phase difference can be nearly zero through reasonable constraints on PCB design. The strategy was applied to the clock bus and achieved good performance, combining with the rules of signal integrity. For the data bus, the timing sequence on source synchronous has been analyzed and the time margin was calculated. The reasonability of the design was verified through the simulation result with Cadence.

Research of Signal Integrality in PCB Design for ARM9 Core Board

2014 ◽  
Vol 644-650 ◽  
pp. 3497-3500
Author(s):  
Liang Yu Su
Keyword(s):  
Embedded System ◽  
Design Process ◽  
High Speed ◽  
Signal Integrity ◽  
Analysis Software ◽  
Pcb Design ◽  
Line Spacing ◽  
Security And Reliability ◽  
Ibis Model

To solve the signal integrity problem which exists in ARM9 core PCB board design is the foundation to ensure high-speed ARM9 embedded system’s security and reliability. This paper make research on reflection, crosstalk and timing issues which exist in the design process of the ARM9 embedded system core PCB board, and perform simulation with the help of Cadence simulation and analysis software and IBIS model. The results show that match impedance is the key to solve the reflection problem,appropriate length and line spacing is help to solve the crosstalk problem,make the clock lines and data lines isometric can effectively reduce the timing issues.

Twisted-Overlap Differential-Pair Approach to Increase Available Layout Space and Reliability in PCB Design

2013 ◽  
Vol 284-287 ◽  
pp. 2531-2537
Author(s):  
Chiu Ching Tuan ◽  
Sun Yen Tan ◽  
Wen Tzeng Huang ◽  
Hung Li Tseng
Keyword(s):  
High Speed ◽  
Signal Integrity ◽  
Great Benefit ◽  
Electronic Products ◽  
Eye Diagram ◽  
Space Requirement ◽  
Pcb Design ◽  
Differential Pair

Modern electronic products require many high-speed differential pairs which require more layout space in PCB design. We propose a twisted-overlap differential-pair (TODP) structure to obtain more routing space and achieve better signal integrity in this study. TODP reduces the layout space requirement by about 25% compared with that required by traditional differential pairs and the twisted differential lines (TDL) structure [2]. Based on an eye diagram performance the TODP design compared to the traditional and TDL designs can improve the peak-to-peak jitter by 26.5% and 12.2%, the overshoot by 14.3% and 2%, the undershoot by 18.8% and 5%, and the eye width by 2 and 1%, respectively. Our results indicate that TODP may be of great benefit in differential-pair PCB design.

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