On improved graph-based alternative wiring scheme for multi-level logic optimization

ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445) ◽

10.1109/icecs.2000.912962 ◽

2002 ◽

Cited By ~ 5

Author(s):

Y.-L. Wu ◽

C.-N. Sze ◽

C.-C. Cheung ◽

H. Fan

Keyword(s):

Logic Optimization ◽

Multi Level

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Multi-Level Logic Optimization

Logic Synthesis and Verification ◽

10.1007/978-1-4615-0817-5_2 ◽

2002 ◽

pp. 29-63 ◽

Cited By ~ 9

Author(s):

Masahiro Fujita ◽

Yusuke Matsunaga ◽

Maciej Ciesielski

Keyword(s):

Logic Optimization ◽

Multi Level

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Multi-level Logic Optimization By Implication Analysis

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629735 ◽

2005 ◽

Cited By ~ 36

Author(s):

W. Kunz

Keyword(s):

Logic Optimization ◽

Multi Level

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Removing hazards in multi-level logic optimization for generalized fundamental-mode asynchronous circuits

2008 IEEE International Conference on Computer Design ◽

10.1109/iccd.2008.4751928 ◽

2008 ◽

Author(s):

Feng Shi

Keyword(s):

Fundamental Mode ◽

Asynchronous Circuits ◽

Logic Optimization ◽

Multi Level

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Multi-level logic optimization based on pseudo maximum sets of permissible functions

1993 European Conference on Design Automation with the European Event in ASIC Design ◽

10.1109/edac.1993.386445 ◽

2002 ◽

Cited By ~ 5

Author(s):

M. Higashida ◽

J. Ishikawa ◽

M. Hiramine ◽

K. Nomura ◽

H. Kumagai ◽

...

Keyword(s):

Logic Optimization ◽

Multi Level

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Boolean decomposition in multi-level logic optimization

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers ◽

10.1109/iccad.1988.122513 ◽

2003 ◽

Cited By ~ 10

Author(s):

S. Devadas ◽

A.R. Wang ◽

A.R. Newton ◽

A. Sangiovanni-Vincentelli

Keyword(s):

Logic Optimization ◽

Multi Level

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Multi-level logic optimization by redundancy addition and removal

1993 European Conference on Design Automation with the European Event in ASIC Design ◽

10.1109/edac.1993.386447 ◽

2002 ◽

Cited By ~ 46

Author(s):

Kwang-Ting Cheng ◽

L.A. Entrena

Keyword(s):

Logic Optimization ◽

Multi Level

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Multi-level logic optimization using binary decision diagrams

1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers ◽

10.1109/iccad.1989.77012 ◽

2003 ◽

Cited By ~ 31

Author(s):

Y. Matsunaga ◽

M. Fujita

Keyword(s):

Binary Decision Diagrams ◽

Decision Diagrams ◽

Binary Decision ◽

Logic Optimization ◽

Multi Level

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Multi-level logic optimization for low power using local logic transformations

Proceedings of International Conference on Computer Aided Design ◽

10.1109/iccad.1996.569643 ◽

2002 ◽

Cited By ~ 13

Author(s):

Q. Wang ◽

S.B.K. Vrudhula

Keyword(s):

Low Power ◽

Logic Optimization ◽

Local Logic ◽

Multi Level

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A heuristic for decomposition in multi-level logic optimization

The Sixth International Conference on VLSI Design ◽

10.1109/icvd.1993.669622 ◽

2005 ◽

Cited By ~ 1

Author(s):

V.K. Singh ◽

A.A. Diwan

Keyword(s):

Logic Optimization ◽

Multi Level

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Multi-level logic optimization for large scale ASICs

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers ◽

10.1109/iccad.1990.129982 ◽

2002 ◽

Cited By ~ 1

Author(s):

A. Nagoya ◽

Y. Nakamura ◽

K. Oguri ◽

R. Nomura

Keyword(s):

Large Scale ◽

Logic Optimization ◽

Multi Level

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