Reduced voltage head room availability for input signal swing is one of the major bottlenecks in the design of circuits operating with low supply voltages which attracts investigations leading to improvement in the input signal dynamic range of such circuits. Employing bulk-driven MOSFETs (BDMOS) at the input section of the circuit is a popular technique used for increasing the input dynamic range, but the smaller bulk transconductance of the bulk-driven MOSFET degrades the performance of the circuit in comparison with that of a conventional gate-driven counterpart. A double tail voltage comparator employing BDMOS technique offering rail-to-rail input dynamic range and capable of operating at sub-1[Formula: see text]V power supply is presented in this paper. A transconductance improvement scheme is employed for the first time in the literature for a voltage comparator to overcome the major drawbacks associated with the reduced bulk transconductance of BDMOS input transistors and double tail topology permits low voltage operation. The performance parameters of the proposed voltage comparator are comparable to that of conventional gate-driven comparators, with an additional advantage of rail-to-rail input dynamic range. Pre-layout and post-layout simulations were performed in Cadence Virtuoso suite with gpdk 90[Formula: see text]nm library at power supply as low as 0.6[Formula: see text]V. The worst case delay of the proposed circuit is 0.71[Formula: see text]ns and the worst case power consumption of the circuit is 15[Formula: see text]uW. The circuit consumes a silicon area of 33[Formula: see text]μm[Formula: see text]46[Formula: see text]μm. An analytical model of the transconductance enhancement technique and delay of the proposed comparator are also presented.
