Design Techniques for Ultra-Low Voltage Comparator Circuits

2014 ◽  
Vol 24 (01) ◽  
pp. 1550013 ◽  
Author(s):  
Yao Wang ◽  
Haibo Wang ◽  
Guangjun Wen
Keyword(s):  
Low Voltage ◽  
Subthreshold Region ◽  
Voltage Comparator ◽  
Low Voltage Operation ◽  
Analytical Results ◽  
Rail To Rail ◽  
Design Techniques

This paper presents a novel low-voltage rail-to-rail comparator circuit and derives optimal transistor size ratios for both conventional latch-based and the proposed comparators which operate in transistor subthreshold region. The obtained analytical results serve well as guidelines for designing low-voltage comparators and the proposed circuit is significantly faster than existing rail-to-rail comparator designs in ultra-low voltage operation.

A Sub-1 V Bulk-Driven Rail to Rail Dynamic Voltage Comparator with Enhanced Transconductance

2021 ◽  
Author(s):  
George M. Joseph ◽  
T. A.Shahul Hameed
Keyword(s):  
Input Signal ◽  
Power Supply ◽  
Dynamic Range ◽  
Low Voltage ◽  
Worst Case ◽  
Additional Advantage ◽  
Silicon Area ◽  
Voltage Comparator ◽  
Low Voltage Operation ◽  
Rail To Rail

Reduced voltage head room availability for input signal swing is one of the major bottlenecks in the design of circuits operating with low supply voltages which attracts investigations leading to improvement in the input signal dynamic range of such circuits. Employing bulk-driven MOSFETs (BDMOS) at the input section of the circuit is a popular technique used for increasing the input dynamic range, but the smaller bulk transconductance of the bulk-driven MOSFET degrades the performance of the circuit in comparison with that of a conventional gate-driven counterpart. A double tail voltage comparator employing BDMOS technique offering rail-to-rail input dynamic range and capable of operating at sub-1[Formula: see text]V power supply is presented in this paper. A transconductance improvement scheme is employed for the first time in the literature for a voltage comparator to overcome the major drawbacks associated with the reduced bulk transconductance of BDMOS input transistors and double tail topology permits low voltage operation. The performance parameters of the proposed voltage comparator are comparable to that of conventional gate-driven comparators, with an additional advantage of rail-to-rail input dynamic range. Pre-layout and post-layout simulations were performed in Cadence Virtuoso suite with gpdk 90[Formula: see text]nm library at power supply as low as 0.6[Formula: see text]V. The worst case delay of the proposed circuit is 0.71[Formula: see text]ns and the worst case power consumption of the circuit is 15[Formula: see text]uW. The circuit consumes a silicon area of 33[Formula: see text]μm[Formula: see text]46[Formula: see text]μm. An analytical model of the transconductance enhancement technique and delay of the proposed comparator are also presented.

scholarly journals A Low-Power, High-Gain Amplifier with Rail-to-Rail Operating Capability: Applications to Biomedical Signal Processing

2021 ◽  
Vol 58 (1) ◽  
pp. 71-76
Author(s):  
Hassan Faraji Baghtash ◽  
Rasoul Pakdel
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Process Variations ◽  
High Gain ◽  
Biomedical Signal Processing ◽  
Noise Power ◽  
Well Performance ◽  
Subthreshold Region ◽  
Rail To Rail ◽  
Unity Gain

low-voltage, low-power, rail-to-rail, two-stage trans-conductance amplifier is presented. The structure exploits body-driven transistors, configured in folded-cascode structure. To reduce the power consumption, the transistors are biased in the subthreshold region. The Specter RF simulation results which are conducted in TSMC 180nm CMOS standard process proves the well-performance of the proposed structure. The performance of the proposed structure against process variations is checked through process corners and Monte Carlo simulations. The results prove the robustness of the proposed amplifier against process uncertainties. Some important specifications of the design derived from circuit simulations are 93.36 dB small-signal gain, 14.4 PV2/Hz input referred noise power, 26.5 kHz unity gain frequency, 20 V/ms slew rate. The proposed structure draws 260 nW power from 0.5 V power supply and is loaded with a 15 pF loading capacitor. The input common mode range of structure is from 0 to 0.5 V.

Current State of Biological High-Resolution Scanning Electron Microscopy

1988 ◽  
Vol 46 ◽  
pp. 180-181 ◽  
Author(s):  
Klaus-Ruediger Peters
Keyword(s):  
High Performance ◽  
Low Voltage ◽  
Backscattered Electrons ◽  
Lens Position ◽  
Low Voltage Operation ◽  
Signal Collection ◽  
Probe Size ◽  
Electron Microscopes ◽  
Scanning Electron Microscopes ◽  
Scanning Electron

A new generation of high performance field emission scanning electron microscopes (FSEM) is now commercially available (JEOL 890, Hitachi S 900, ISI OS 130-F) characterized by an "in lens" position of the specimen where probe diameters are reduced and signal collection improved. Additionally, low voltage operation is extended to 1 kV. Compared to the first generation of FSEM (JE0L JSM 30, Hitachi S 800), which utilized a specimen position below the final lens, specimen size had to be reduced but useful magnification could be impressively increased in both low (1-4 kV) and high (5-40 kV) voltage operation, i.e. from 50,000 to 200,000 and 250,000 to 1,000,000 x respectively.At high accelerating voltage and magnification, contrasts on biological specimens are well characterized1 and are produced by the entering probe electrons in the outmost surface layer within -vl nm depth. Backscattered electrons produce only a background signal. Under these conditions (FIG. 1) image quality is similar to conventional TEM (FIG. 2) and only limited at magnifications >1,000,000 x by probe size (0.5 nm) or non-localization effects (%0.5 nm).

High resolution at low voltage: A new approach

1989 ◽  
Vol 47 ◽  
pp. 76-77
Author(s):  
Arthur V. Jones
Keyword(s):  
Low Voltage ◽  
Emission Sources ◽  
New Approach ◽  
Design Concepts ◽  
Probe Diameter ◽  
Low Voltage Operation ◽  
Sufficient Intensity ◽  
Electron Microscopes ◽  
Scanning Electron Microscopes ◽  
Immersion Type

With the introduction of field-emission sources and “immersion-type” objective lenses, the resolution obtainable with modern scanning electron microscopes is approaching that obtainable in STEM and TEM-but only with specific types of specimens. Bulk specimens still suffer from the restrictions imposed by internal scattering and the need to be conducting. Advances in coating techniques have largely overcome these problems but for a sizeable body of specimens, the restrictions imposed by coating are unacceptable.For such specimens, low voltage operation, with its low beam penetration and freedom from charging artifacts, is the method of choice.Unfortunately the technical dificulties in producing an electron beam sufficiently small and of sufficient intensity are considerably greater at low beam energies — so much so that a radical reevaluation of convential design concepts is needed.The probe diameter is usually given by

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Low-voltage operation of the organic thin film transistor with a diagonal configuration

2003 ◽  
Author(s):  
Toshihide Kamata ◽  
Manabu Yoshida ◽  
Sei Uemura ◽  
Satoshi Hoshino ◽  
Noriyuki Takada ◽  
...  
Keyword(s):  
Thin Film ◽  
Low Voltage ◽  
Thin Film Transistor ◽  
Organic Thin Film ◽  
Organic Thin Film Transistor ◽  
Low Voltage Operation
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