A Sub-1 V Bulk-Driven Rail to Rail Dynamic Voltage Comparator with Enhanced Transconductance

2021 ◽  
Author(s):  
George M. Joseph ◽  
T. A.Shahul Hameed
Keyword(s):  
Input Signal ◽  
Power Supply ◽  
Dynamic Range ◽  
Low Voltage ◽  
Worst Case ◽  
Additional Advantage ◽  
Silicon Area ◽  
Voltage Comparator ◽  
Low Voltage Operation ◽  
Rail To Rail

Reduced voltage head room availability for input signal swing is one of the major bottlenecks in the design of circuits operating with low supply voltages which attracts investigations leading to improvement in the input signal dynamic range of such circuits. Employing bulk-driven MOSFETs (BDMOS) at the input section of the circuit is a popular technique used for increasing the input dynamic range, but the smaller bulk transconductance of the bulk-driven MOSFET degrades the performance of the circuit in comparison with that of a conventional gate-driven counterpart. A double tail voltage comparator employing BDMOS technique offering rail-to-rail input dynamic range and capable of operating at sub-1[Formula: see text]V power supply is presented in this paper. A transconductance improvement scheme is employed for the first time in the literature for a voltage comparator to overcome the major drawbacks associated with the reduced bulk transconductance of BDMOS input transistors and double tail topology permits low voltage operation. The performance parameters of the proposed voltage comparator are comparable to that of conventional gate-driven comparators, with an additional advantage of rail-to-rail input dynamic range. Pre-layout and post-layout simulations were performed in Cadence Virtuoso suite with gpdk 90[Formula: see text]nm library at power supply as low as 0.6[Formula: see text]V. The worst case delay of the proposed circuit is 0.71[Formula: see text]ns and the worst case power consumption of the circuit is 15[Formula: see text]uW. The circuit consumes a silicon area of 33[Formula: see text]μm[Formula: see text]46[Formula: see text]μm. An analytical model of the transconductance enhancement technique and delay of the proposed comparator are also presented.

Design Techniques for Ultra-Low Voltage Comparator Circuits

2014 ◽  
Vol 24 (01) ◽  
pp. 1550013 ◽  
Author(s):  
Yao Wang ◽  
Haibo Wang ◽  
Guangjun Wen
Keyword(s):  
Low Voltage ◽  
Subthreshold Region ◽  
Voltage Comparator ◽  
Low Voltage Operation ◽  
Analytical Results ◽  
Rail To Rail ◽  
Design Techniques

This paper presents a novel low-voltage rail-to-rail comparator circuit and derives optimal transistor size ratios for both conventional latch-based and the proposed comparators which operate in transistor subthreshold region. The obtained analytical results serve well as guidelines for designing low-voltage comparators and the proposed circuit is significantly faster than existing rail-to-rail comparator designs in ultra-low voltage operation.

A 0.6V 19.5μW 80dB DR ΔΣ Modulator with SA-Quantizers and Digital Feedforward Path

2017 ◽  
Vol 26 (07) ◽  
pp. 1750117 ◽  
Author(s):  
Hongmei Chen ◽  
Li Wang ◽  
Ting Li ◽  
Lin He ◽  
Fujiang Lin
Keyword(s):  
Input Signal ◽  
Dynamic Range ◽  
Low Voltage ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Dynamic Element Matching ◽  
Loop Filter ◽  
Op Amp ◽  
Low Voltage Operation ◽  
Delta Sigma

This paper presents a discrete-time multi-bit Delta–Sigma modulator employing successive approximation (SA)-quantizers for bio-signal acquisitions. In the proposed [Formula: see text] modulator, the input signal is separately quantized and the signal summation is performed in the digital domain to avoid the power hungry analog adder. Two SA-quantizers are used in this modulator. One is dedicated to quantize the input signal and the other is to quantize the summation of the integrators’ outputs. Dynamic Element Matching (DEM) technique is used to mitigate the mismatch among the digital-to-analog conversion (DAC) elements. To reduce the complexity of the DEM logic, the 7-bit summed quantizer output is truncated into a 5-bit code before it is fed to the DEM circuits. Double tailed inverter-based op-amp is used in the loop filter for low-voltage operation. Correlated-double-sampling is adopted to enhance the effective gain of the integrator. The proposed modulator is designed and fabricated in a 130-nm CMOS technology. The measurement result shows that the modulator achieves a dynamic range of 80[Formula: see text]dB, a peak SNDR of 77[Formula: see text]dB in a 25[Formula: see text]kHz signal bandwidth at sampling rate of 800[Formula: see text]kHz. The prototype modulator occupies 0.25[Formula: see text]mm2 and consumes only 19.5[Formula: see text][Formula: see text]W from a 0.6[Formula: see text]V supply. The proposed modulator achieves a figure of merit of 67 fJ per conversion step.

TUNABLE ACTIVE FILTERS FOR RF AND MICROWAVE APPLICATIONS

2014 ◽  
Vol 23 (06) ◽  
pp. 1450088 ◽  
Author(s):  
LEONARDO PANTOLI ◽  
VINCENZO STORNELLI ◽  
GIORGIO LEUZZI
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Bandpass Filter ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Active Filters ◽  
Center Frequency ◽  
Power Supply Voltage ◽  
Microwave Applications

In this paper, we present a low-voltage tunable active filter for microwave applications. The proposed filter is based on a single-transistor active inductor (AI), that allows the reduction of circuit area and power consumption. The three active-cell bandpass filter has a 1950 MHz center frequency with a -1 dB flat bandwidth of 10 MHz (Q ≈ 200), a shape factor (30–3 dB) of 2.5, and can be tuned in the range 1800–2050 MHz, with constant insertion loss. A dynamic range of about 75 dB is obtained, with a P1dB compression point of -5 dBm. The prototype board, fabricated on a TLX-8 substrate, has a 4 mW power consumption with a 1.2 V power supply voltage.

ADDRESSING MEMORY EFFECT FOR RAIL-TO-RAIL COMPARATOR WITH NEAR-THRESHOLD SUPPLY VOLTAGE

2013 ◽  
Vol 22 (06) ◽  
pp. 1350048 ◽  
Author(s):  
SARAVANAN RAMAMOORTHY ◽  
HAIBO WANG
Keyword(s):  
Memory Effect ◽  
Threshold Voltage ◽  
Power Supply ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Design Modification ◽  
Offset Voltage ◽  
Rail To Rail ◽  
Near Threshold

Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impacts of the proposed design modification on comparator speed, offset voltage and power consumptions are discussed. Based on a 0.13 μm CMOS technology and with a 0.5 V power supply, the proposed comparator is compared with the original comparator in terms of memory effect, speed, power consumption and input offset voltage. The integral and differential nonlinearity (INL and DNL) of 10-bit SAR ADCs with using the proposed and original comparators are also compared.

Current State of Biological High-Resolution Scanning Electron Microscopy

1988 ◽  
Vol 46 ◽  
pp. 180-181 ◽  
Author(s):  
Klaus-Ruediger Peters
Keyword(s):  
High Performance ◽  
Low Voltage ◽  
Backscattered Electrons ◽  
Lens Position ◽  
Low Voltage Operation ◽  
Signal Collection ◽  
Probe Size ◽  
Electron Microscopes ◽  
Scanning Electron Microscopes ◽  
Scanning Electron

A new generation of high performance field emission scanning electron microscopes (FSEM) is now commercially available (JEOL 890, Hitachi S 900, ISI OS 130-F) characterized by an "in lens" position of the specimen where probe diameters are reduced and signal collection improved. Additionally, low voltage operation is extended to 1 kV. Compared to the first generation of FSEM (JE0L JSM 30, Hitachi S 800), which utilized a specimen position below the final lens, specimen size had to be reduced but useful magnification could be impressively increased in both low (1-4 kV) and high (5-40 kV) voltage operation, i.e. from 50,000 to 200,000 and 250,000 to 1,000,000 x respectively.At high accelerating voltage and magnification, contrasts on biological specimens are well characterized1 and are produced by the entering probe electrons in the outmost surface layer within -vl nm depth. Backscattered electrons produce only a background signal. Under these conditions (FIG. 1) image quality is similar to conventional TEM (FIG. 2) and only limited at magnifications >1,000,000 x by probe size (0.5 nm) or non-localization effects (%0.5 nm).

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