Reconfigurable cache memory architecture design based on VHDL

2017 International Conference on Electrical and Computing Technologies and Applications (ICECTA) ◽

10.1109/icecta.2017.8251964 ◽

2017 ◽

Author(s):

Safaa S. Omran ◽

Ibrahim A. Amory

Keyword(s):

Cache Memory ◽

Architecture Design ◽

Memory Architecture ◽

Reconfigurable Cache

Download Full-text

Analysis of Cache Memory Architecture Design Using Low-Power Reduction Techniques for Microprocessors

10.1007/978-981-16-4222-7_56 ◽

2021 ◽

pp. 495-503

Author(s):

Reeya Agrawal

Keyword(s):

Low Power ◽

Power Reduction ◽

Cache Memory ◽

Architecture Design ◽

Memory Architecture ◽

Reduction Techniques

Download Full-text

Reconfigurable cache memory architecture for integral image and integral histogram applications

2011 IEEE Workshop on Signal Processing Systems (SiPS) ◽

10.1109/sips.2011.6088966 ◽

2011 ◽

Author(s):

Po-Hao Hsu ◽

Shao-Yi Chien

Keyword(s):

Cache Memory ◽

Memory Architecture ◽

Integral Image ◽

Integral Histogram ◽

Reconfigurable Cache

Download Full-text

A new perspective on processing-in-memory architecture design

Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness - MSPC '13 ◽

10.1145/2492408.2492418 ◽

2013 ◽

Author(s):

Dong Ping Zhang ◽

Nuwan Jayasena ◽

Alexander Lyashevsky ◽

Joseph Greathouse ◽

Mitesh Meswani ◽

...

Keyword(s):

Architecture Design ◽

Memory Architecture ◽

New Perspective

Download Full-text

Cache Memory Architecture for Core Processor

10.1007/978-981-16-5207-3_66 ◽

2021 ◽

pp. 809-820

Author(s):

Reeya Agrawal

Keyword(s):

Cache Memory ◽

Memory Architecture

Download Full-text

Split Memory Based Memory Architecture with Single-ended High Speed Sensing Circuit to Improve Cache Memory Performance

2020 6th International Conference on Signal Processing and Communication (ICSC) ◽

10.1109/icsc48311.2020.9182771 ◽

2020 ◽

Author(s):

Kirmender Singh ◽

Sajal Khanna

Keyword(s):

Memory Performance ◽

Cache Memory ◽

Memory Architecture

Download Full-text

An Edge Cache Memory Architecture for Early Visual Processing VLSIs

10.7567/ssdm.2006.p-5-5 ◽

2006 ◽

Author(s):

Ovgu Ozturk ◽

Tadashi Shibata

Keyword(s):

Visual Processing ◽

Cache Memory ◽

Memory Architecture ◽

Early Visual Processing

Download Full-text

A Class Project For Low Power Cache Memory Architecture

10.18260/1-2--6 ◽

2020 ◽

Author(s):

Yul Chu

Keyword(s):

Low Power ◽

Cache Memory ◽

Memory Architecture ◽

Download Full-text

A 16GHz Optical Cache Memory Architecture for Set-Associative Mapping in Chip Multiprocessors

Optical Fiber Communication Conference ◽

10.1364/ofc.2014.th2a.6 ◽

2014 ◽

Author(s):

P. Maniotis ◽

D. Fitsios ◽

G.T. Kanellos ◽

N. Pleros

Keyword(s):

Chip Multiprocessors ◽

Cache Memory ◽

Memory Architecture

Download Full-text

Comparative Study of Reconfigurable Cache Memory

10.24086/cocos17.01 ◽

2017 ◽

Author(s):

Ibrahim Amory ◽

Safaa Omran

Keyword(s):

Comparative Study ◽

Cache Memory ◽

Reconfigurable Cache

Download Full-text

Analysis of MTCMOS Cache Memory Architecture for Processor

Proceedings of International Conference on Communication and Artificial Intelligence - Lecture Notes in Networks and Systems ◽

10.1007/978-981-33-6546-9_9 ◽

2021 ◽

pp. 81-91

Author(s):

Reeya Agrawal ◽

Vishal Goyal

Keyword(s):

Cache Memory ◽

Memory Architecture

Download Full-text