Analysis of Cache Memory Architecture Design Using Low-Power Reduction Techniques for Microprocessors

Mapping Intimacies ◽

10.1007/978-981-16-4222-7_56 ◽

2021 ◽

pp. 495-503

Author(s):

Reeya Agrawal

Keyword(s):

Low Power ◽

Power Reduction ◽

Cache Memory ◽

Architecture Design ◽

Memory Architecture ◽

Reduction Techniques

Download Full-text

A Class Project For Low Power Cache Memory Architecture

10.18260/1-2--6 ◽

2020 ◽

Author(s):

Yul Chu

Keyword(s):

Low Power ◽

Cache Memory ◽

Memory Architecture ◽

Download Full-text

Standby power reduction techniques for ultra-low power processors

ESSCIRC 2008 - 34th European Solid-State Circuits Conference ◽

10.1109/esscirc.2008.4681823 ◽

2008 ◽

Author(s):

Yoonmyung Lee ◽

Mingoo Seok ◽

Scott Hanson ◽

David Blaauw ◽

Dennis Sylvester

Keyword(s):

Low Power ◽

Power Reduction ◽

Ultra Low Power ◽

Reduction Techniques ◽

Download Full-text

Low Power Single Bit Cache Memory Architecture

Materials Today Proceedings ◽

10.1016/j.matpr.2021.02.725 ◽

2021 ◽

Author(s):

Reeya Agrawal ◽

Manish Kumar

Keyword(s):

Low Power ◽

Cache Memory ◽

Memory Architecture

Download Full-text

Reconfigurable cache memory architecture design based on VHDL

2017 International Conference on Electrical and Computing Technologies and Applications (ICECTA) ◽

10.1109/icecta.2017.8251964 ◽

2017 ◽

Author(s):

Safaa S. Omran ◽

Ibrahim A. Amory

Keyword(s):

Cache Memory ◽

Architecture Design ◽

Memory Architecture ◽

Reconfigurable Cache

Download Full-text

Implementation and Analysis of Low Power Reduction Techniques in Sense Amplifier

2018 Second International Conference on Electronics, Communication and Aerospace Technology (ICECA) ◽

10.1109/iceca.2018.8474703 ◽

2018 ◽

Author(s):

Reeya Agrawal ◽

V. K. Tomar

Keyword(s):

Low Power ◽

Power Reduction ◽

Sense Amplifier ◽

Reduction Techniques

Download Full-text

Best practices in low power design. 1. Power reduction techniques [Tutorial 1]

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. ◽

10.1109/iccad.2004.1382523 ◽

2005 ◽

Author(s):

E. Mocii ◽

M. Pedram

Keyword(s):

Best Practices ◽

Low Power ◽

Low Power Design ◽

Power Reduction ◽

Reduction Techniques

Download Full-text

Low-Power High-Performance and Dynamically Configured Multi-Port Cache Memory Architecture

2007 International Conference on Electrical Engineering ◽

10.1109/icee.2007.4287320 ◽

2007 ◽

Author(s):

H. Bajwa ◽

X. Chen

Keyword(s):

Low Power ◽

High Performance ◽

Cache Memory ◽

Memory Architecture

Download Full-text

Analysis of Low Power Reduction Techniques on Cache(SRAM) Memory

2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT) ◽

10.1109/icccnt.2018.8494021 ◽

2018 ◽

Author(s):

Reeya Agrawal ◽

Vinay Kumar Tomar

Keyword(s):

Low Power ◽

Power Reduction ◽

Reduction Techniques ◽

Download Full-text

Low Power Single-Bit Cache Memory Architecture

IOP Conference Series Materials Science and Engineering ◽

10.1088/1757-899x/1116/1/012136 ◽

2021 ◽

Vol 1116 (1) ◽

pp. 012136

Author(s):

Reeya Agrawal ◽

Neetu Faujdar ◽

Aditi Saxena

Keyword(s):

Low Power ◽

Cache Memory ◽

Memory Architecture

Download Full-text

Design and comparative analysis of low power 64 Bit SRAM and its peripherals using power reduction techniques

2016 5th International Conference on Wireless Networks and Embedded Systems (WECON) ◽

10.1109/wecon.2016.7993473 ◽

2016 ◽

Author(s):

Gaurav Vashisht ◽

Hitesh Pahuja ◽

Batwinder Singh ◽

Sudhakar Panday

Keyword(s):

Comparative Analysis ◽

Low Power ◽

Power Reduction ◽

Reduction Techniques

Download Full-text