Hardware Implementation of 24-bit Vedic Multiplier in 32-bit Floating-Point Divider

Author(s):  
C R S Hanuman ◽  
J Kamala
Author(s):  
Jean-Michel Muller ◽  
Nicolas Brunie ◽  
Florent de Dinechin ◽  
Claude-Pierre Jeannerod ◽  
Mioara Joldes ◽  
...  

Multipliers play crucial role in present days in the area of digital signal processing and in communication systems applications. The entire system performance depends on speed area and power of the multipliers. In our paper, we developed a 64x64 bit complex floating-point multiplier with 64bit IEEE 754 format multipliers having less delay. Vedic multiplier of ripple carry adder based is suggested for mantissa multiplication in IEEE 754 format. Suggested Vedic multiplier uses historic Vedic Indian mathematics sutra called UrdhvaTiryagbhyam for Vedic multiplication. The architecture Proposed for 64x64 bit complex floating-point multiplier is in Xilinx ISE 14.2 FPGA navigator in Verilog HDL. Eventually, the outcomes of the suggested multiplier will differentiate with traditional booth multiplier and array multiplier which represents clearly that complex multiplication using suggested architecture gives less delay, power and low area.


Author(s):  
Jean-Michel Muller ◽  
Nicolas Brisebarre ◽  
Florent de Dinechin ◽  
Claude-Pierre Jeannerod ◽  
Vincent Lefèvre ◽  
...  

2014 ◽  
Vol 2014 ◽  
pp. 1-12 ◽  
Author(s):  
Spencer Fowers ◽  
Alok Desai ◽  
Dah-Jye Lee ◽  
Dan Ventura ◽  
James Archibald

This paper presents a novel feature descriptor called TreeBASIS that provides improvements in descriptor size, computation time, matching speed, and accuracy. This new descriptor uses a binary vocabulary tree that is computed using basis dictionary images and a test set of feature region images. To facilitate real-time implementation, a feature region image is binary quantized and the resulting quantized vector is passed into the BASIS vocabulary tree. A Hamming distance is then computed between the feature region image and theeffectively descriptive basis dictionary imageat a node to determine the branch taken and the path the feature region image takes is saved as a descriptor. The TreeBASIS feature descriptor is an excellent candidate for hardware implementation because of its reduced descriptor size and the fact that descriptors can be created and features matched without the use of floating point operations. The TreeBASIS descriptor is more computationally and space efficient than other descriptors such as BASIS, SIFT, and SURF. Moreover, it can be computed entirely in hardware without the support of a CPU for additional software-based computations. Experimental results and a hardware implementation show that the TreeBASIS descriptor compares well with other descriptors for frame-to-frame homography computation while requiring fewer hardware resources.


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