Low-voltage limitations and challenges of nano-scale CMOS LSIs - A personal view of memory designer -

Author(s):  
Kiyoo Itoh
Keyword(s):  
2009 ◽  
Vol 53 (4) ◽  
pp. 402-410 ◽  
Author(s):  
Kiyoo Itoh ◽  
Masashi Horiguchi

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