An artificial neural network guided parallel genetic approach to the routing problem for field programmable gate arrays

2002 ◽  
Author(s):  
A. Muthukaruppan ◽  
S. Suresh ◽  
B.S.N. Rao ◽  
V. Kamakoti
Keyword(s):  
Neural Network ◽  
Artificial Neural Network ◽  
Field Programmable Gate Arrays ◽  
Genetic Approach ◽  
Routing Problem ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Artificial Neural

HARDWARE IMPLEMENTATION OF A NEW ARTIFICIAL NEURON

2005 ◽  
Vol 15 (06) ◽  
pp. 427-433 ◽  
Author(s):  
RICHARD LABIB ◽  
FRANCIS AUDETTE ◽  
ALEXANDRE FORTIN ◽  
REZA ASSADI
Keyword(s):  
Neural Network ◽  
Hardware Implementation ◽  
Field Programmable Gate Arrays ◽  
External Temperature ◽  
Artificial Neuron ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
New Type ◽  
Software And Hardware

This paper describes an FPGA (Field Programmable Gate Arrays) implementation of a new type of neuron, the Quantron. The goal is to demonstrate the capability of current technology to closely recreate the human body's reaction to a change of temperature. This is accomplished by creating a function that adds a number of kernels at different frequencies depending on the external temperature. Once the sum of the kernels reaches a certain threshold, the artificial neural network, equivalent to its biological counterpart, "reacts" by sending a specific output signal designed to trigger a response. The various elements of each subsystem are discussed and implemented in software and hardware. The results are analyzed in terms of accuracy and efficiency compared to the biological equivalent.

A Multilevel Pseudo-Boolean Satisfiability-Based Approach for Segmented Channel Routing

2015 ◽  
Vol 24 (06) ◽  
pp. 1550083
Author(s):  
Dahua Zhang ◽  
Wei Li ◽  
Tao Du
Keyword(s):  
Optimization Technique ◽  
Field Programmable Gate Arrays ◽  
Boolean Satisfiability ◽  
Channel Routing ◽  
Routing Problem ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Np Complete ◽  
Boolean Optimization

The segmented channel routing problem is fundamental to the routing of row-based field programmable gate arrays (FPGAs) and is proven to be nondeterministic polynomial time (NP) complete. In this paper, we capitalize on the compelling advancements in satisfiability (SAT) solvers to propose a multilevel pseudo-Boolean SAT-based approach. We construct several levels of hierarchy amongst the nets and the routing problem of each level is formulated as a pseudo-Boolean optimization (PBO) problem. Moreover, an optimization technique of reducing the number of variables in PBO problems is described to improve the scalability of the proposed method. Similar to the SAT-based routing, the unroutability of a given circuit can be proved by the approach. Experimental results show that the proposed method compares very favorably with existing algorithms and achieves the best convergence rate.

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