Hardware implementation of an artificial neural network using field programmable gate arrays (FPGA's)

1994 ◽  
Vol 41 (6) ◽  
pp. 665-667 ◽  
Author(s):  
N.M. Botros ◽  
M. Abdul-Aziz
Keyword(s):  
Neural Network ◽  
Artificial Neural Network ◽  
Hardware Implementation ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Artificial Neural

HARDWARE IMPLEMENTATION OF A NEW ARTIFICIAL NEURON

2005 ◽  
Vol 15 (06) ◽  
pp. 427-433 ◽  
Author(s):  
RICHARD LABIB ◽  
FRANCIS AUDETTE ◽  
ALEXANDRE FORTIN ◽  
REZA ASSADI
Keyword(s):  
Neural Network ◽  
Hardware Implementation ◽  
Field Programmable Gate Arrays ◽  
External Temperature ◽  
Artificial Neuron ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
New Type ◽  
Software And Hardware

This paper describes an FPGA (Field Programmable Gate Arrays) implementation of a new type of neuron, the Quantron. The goal is to demonstrate the capability of current technology to closely recreate the human body's reaction to a change of temperature. This is accomplished by creating a function that adds a number of kernels at different frequencies depending on the external temperature. Once the sum of the kernels reaches a certain threshold, the artificial neural network, equivalent to its biological counterpart, "reacts" by sending a specific output signal designed to trigger a response. The various elements of each subsystem are discussed and implemented in software and hardware. The results are analyzed in terms of accuracy and efficiency compared to the biological equivalent.

scholarly journals Pattern Classification of Fabric Defects Using a Probabilistic Neural Network and Its Hardware Implementation using the Field Programmable Gate Array System

2017 ◽  
Vol 25 (0) ◽  
pp. 42-48 ◽  
Author(s):  
Abul Hasnat ◽  
Anindya Ghosh ◽  
Amina Khatun ◽  
Santanu Halder
Keyword(s):  
Neural Network ◽  
Hardware Implementation ◽  
Probabilistic Neural Network ◽  
Clock Period ◽  
Data Set ◽  
Gate Arrays ◽  
Hardware System ◽  
Field Programmable ◽  
Programmable Gate Arrays

This study proposes a fabric defect classification system using a Probabilistic Neural Network (PNN) and its hardware implementation using a Field Programmable Gate Arrays (FPGA) based system. The PNN classifier achieves an accuracy of 98 ± 2% for the test data set, whereas the FPGA based hardware system of the PNN classifier realises about 94±2% testing accuracy. The FPGA system operates as fast as 50.777 MHz, corresponding to a clock period of 19.694 ns.

scholarly journals Designing and Implementing FPGA for AES

2019 ◽  
Vol 8 (11S) ◽  
pp. 953-955
Keyword(s):  
Hardware Implementation ◽  
Field Programmable Gate Arrays ◽  
Hardware Platform ◽  
Memory Space ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Encryption Method ◽  
Low Charge

The execution of DES and triple DES is not possible on hardware platform because they consume huge memory space. We can use field programmable gate arrays in order to do the hardware implementation because of its low charge, advertising space and reconfiguration nature. This paper aims at reducing the delay by using pipeline for speeding up the process. The proposed pipeline structure has a characteristic of having round keys which during iterations of encryption are utilized and an encryption method is used for generating them in parallel. The overall delay related to a delay of coding of plaintext block is reduced. The simulation is done in VHDL by Xilinx and implementation is done on FPGA Spartan 3E.

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