An Improved Performance Ka-Band Low Noise Amplifier and On-Chip Transmission Line Modeling in 0.18 μm CMOS Technology

Author(s):  
Mehran Hazer-Sahlabadi ◽  
Abdolali Abdipour ◽  
Abbas Mohammadi
Author(s):  
Xiangyu Liang ◽  
Liguo Sun ◽  
Dongwei Pang ◽  
Shiwei Wu

2011 ◽  
Vol 53 (5) ◽  
pp. 1131-1134
Author(s):  
Hsien-Chin Chiu ◽  
Ting-Huei Chen ◽  
Jeffrey S. Fu ◽  
T. A. Nirmalathas

Frequenz ◽  
2013 ◽  
Vol 67 (1-2) ◽  
Author(s):  
Hojjat Babaei Kia ◽  
Abu Khari A'ain

AbstractThis paper presents the design of a single-ended input, differential output low noise amplifier for GPS applications in 0.18 µm CMOS technology. This Low Noise Amplifier (LNA) is composed of a common source (CS) amplifier adopted with a common gate, common source (CGCS) balun load. Instead of spiral on-chip inductor, a differential active inductor circuit (DAI) is used as an active load of balun and also


2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  


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