On the hierarchical design of VLSI processor arrays

2003 ◽  
Author(s):  
L. Thiele
Keyword(s):  
Hierarchical Design ◽  
Processor Arrays

DESIGN OF A MULTI-LEVEL FAULT-TOLERANT MESH (MFTM) FOR HIGH RELIABILITY APPLICATIONS

1995 ◽  
Vol 02 (04) ◽  
pp. 419-429
Author(s):  
SHAMBHU J. UPADHYAYA ◽  
I-SHYAN HWANG
Keyword(s):  
System Reliability ◽  
Fault Tolerant ◽  
High Reliability ◽  
Operational Reliability ◽  
Variable Number ◽  
Hierarchical Design ◽  
Processor Arrays ◽  
Design Paradigm ◽  
Multi Level ◽  
Overall Reliability

This paper presents a novel technique for the enhancement of operational reliability of processor arrays by a multi-level fault-tolerant design approach. The key idea of the design is based on the well known hierarchical design paradigm. The proposed fault-tolerant architecture uses a flexible reconfiguration of redundant nodes, thereby offering a better spare utilization than existing two-level redundancy schemes. A variable number of spares is provided at each level of redundancy which enables a flexible reconfiguration as well as area efficient layouts and better spare utilization. The spare nodes at each level can replace any of the failed primary nodes, not only at the same level but also those at the lower levels. The architecture can be adopted to increase the system reliability in Multi Chip Modules (MCMs). The main contributions of our work are the higher degree of fault tolerance, higher overall reliability, flexibility, and a better spare utilization.

scholarly journals Visual Odometry for Pixel Processor Arrays

2017 ◽  
Author(s):  
Laurie Bose ◽  
Jianing Chen ◽  
Stephen J. Carey ◽  
Piotr Dudek ◽  
Walterio Mayol-Cuevas
Keyword(s):  
Visual Odometry ◽  
Processor Arrays

scholarly journals Hierarchical Design Rewriting with Maude

2009 ◽  
Vol 238 (3) ◽  
pp. 45-62 ◽  
Author(s):  
Roberto Bruni ◽  
Alberto Lluch Lafuente ◽  
Ugo Montanari
Keyword(s):  
Hierarchical Design

Research and Simulation of Energy-Saving Hierarchical Design Model for Differentiate Architecture

2014 ◽  
Vol 986-987 ◽  
pp. 1026-1028
Author(s):  
Hai Qing Guo
Keyword(s):  
Energy Saving ◽  
Building Energy ◽  
Indicator System ◽  
Building Envelope ◽  
Design Model ◽  
Current Status ◽  
Building Energy Efficiency ◽  
Hierarchical Design ◽  
Evaluation Information

Energy-saving hierarchical design model is established for differentiate architecture. From current status of China's construction, exploration research is established on energy-saving hierarchical design model of differentiate architecture to evaluate indicator system of energy-saving building. Availability of evaluation information in index system is low, so it is difficult to play the role of evaluation of building energy-efficiency. EHTV difference method is used to calculate and evaluate energy-saving design of hierarchical building, including: heat transfer indicator of building envelope targets, air conditioning and heating consumption, basis of EHTV indicators.

Hierarchical power management for adaptive tightly-coupled processor arrays

2013 ◽  
Vol 18 (1) ◽  
pp. 1-25 ◽  
Author(s):  
Vahid Lari ◽  
Shravan Muddasani ◽  
Srinivas Boppu ◽  
Frank Hannig ◽  
Moritz Schmid ◽  
...  
Keyword(s):  
Power Management ◽  
Processor Arrays ◽  
Tightly Coupled ◽  
Hierarchical Power Management
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