Hierarchical parameterized synthesis of semi regular VLSI processor arrays

1991., IEEE International Sympoisum on Circuits and Systems ◽

10.1109/iscas.1991.176319 ◽

2002 ◽

Cited By ~ 1

Author(s):

A.A.J. de Lange ◽

E.F. Deprettere ◽

P.M. Dewilde

Keyword(s):

Processor Arrays

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Processor arrays for two-dimensional discrete Fourier transform

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1993.0014 ◽

1993 ◽

Vol 140 (2) ◽

pp. 101

Author(s):

D.V. Korchev ◽

Ju.S. Kanevsky

Keyword(s):

Fourier Transform ◽

Discrete Fourier Transform ◽

Two Dimensional ◽

Processor Arrays

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Visual Odometry for Pixel Processor Arrays

2017 IEEE International Conference on Computer Vision (ICCV) ◽

10.1109/iccv.2017.493 ◽

2017 ◽

Cited By ~ 6

Author(s):

Laurie Bose ◽

Jianing Chen ◽

Stephen J. Carey ◽

Piotr Dudek ◽

Walterio Mayol-Cuevas

Keyword(s):

Visual Odometry ◽

Processor Arrays

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Hierarchical power management for adaptive tightly-coupled processor arrays

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2390191.2390193 ◽

2013 ◽

Vol 18 (1) ◽

pp. 1-25 ◽

Cited By ~ 13

Author(s):

Vahid Lari ◽

Shravan Muddasani ◽

Srinivas Boppu ◽

Frank Hannig ◽

Moritz Schmid ◽

...

Keyword(s):

Power Management ◽

Processor Arrays ◽

Tightly Coupled ◽

Hierarchical Power Management

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On the hierarchical design of VLSI processor arrays

10.1109/iscas.1988.15454 ◽

2003 ◽

Cited By ~ 25

Author(s):

L. Thiele

Keyword(s):

Hierarchical Design ◽

Processor Arrays

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A parallelizing method for implementing image processing tasks on SIMD linear processor arrays

Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97 ◽

10.1109/camp.1997.631944 ◽

2002 ◽

Cited By ~ 8

Author(s):

S. Kyo ◽

S. Okazaki ◽

Y. Fujita ◽

N. Yamashita

Keyword(s):

Image Processing ◽

Processor Arrays

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Parallel AES Encryption Engines for Many-Core Processor Arrays

IEEE Transactions on Computers ◽

10.1109/tc.2011.251 ◽

2013 ◽

Vol 62 (3) ◽

pp. 536-547 ◽

Cited By ~ 48

Author(s):

Bin Liu ◽

Bevan M. Baas

Keyword(s):

Processor Arrays ◽

Many Core

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Memory-coupled processor arrays for a broad spectrum of applications

WOPPLOT 83 Parallel Processing: Logic, Organization, and Technology - Lecture Notes in Physics ◽

10.1007/bfb0018261 ◽

2005 ◽

pp. 158-177 ◽

Cited By ~ 1

Author(s):

Gerhard Fritsch

Keyword(s):

Broad Spectrum ◽

Processor Arrays

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A PARALLEL ALGORITHM TO GENERATE N-ARY REFLECTED GRAY CODES IN A LINEAR ARRAY WITH RECONFIGURABLE BUS SYSTEM

Parallel Processing Letters ◽

10.1142/s0129626493000198 ◽

1993 ◽

Vol 03 (02) ◽

pp. 157-164 ◽

Cited By ~ 2

Author(s):

P. THANGAVEL ◽

V.P. MUTHUSWAMY

Keyword(s):

Parallel Algorithm ◽

Linear Array ◽

Constant Time ◽

Processor Array ◽

Gray Codes ◽

System A ◽

Processor Arrays ◽

Bus System

A simple parallel algorithm for generating N-ary reflected Gray codes is presented. The algorithm is derived from the pattern of N-ary reflected Gray codes. The algorithm runs on a linear processor array with a reconfigurable bus system. A reconfigurable bus system is a bus system whose configuration can be dynamically changed. Recently processor arrays with reconfigurable bus systems were used to solve many problems in constant time. There already exists experimental reconfigurable chips.

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