Background:
Advance communication systems require new techniques for FIR filters
with resource efficiency in terms of high performance and low power consumption. Lowcomplexity
architectures are required by FIR filters for implementation in field programmable gate
Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have
low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated.
Objective:
The implementation and application of high tap FIR filters by a partial product reduce
this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture
with FPGA.
Method:
The proposed technique FIR filter is based on a new architecture method and implemented
using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded
in Verilog HDL and the code developed from the proposed architecture has been simulated using
Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit
techniques are used to further improve power and performance. In addition, the proposed architecture
achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented
on the proposed architecture.
Results:
The design’s example demonstrates a 25% reduction in resource usage compared to existing
reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture
is 37% faster than the best performance of existing methods.
Conclusion:
The proposed architecture offers low power and improved speed with the lowcomplexity
design that gives the best architecture FIR filter for both reconfigurable and fixed applications.
An efficient FIR filter architecture
