Efficient FIR Filter Architecture using FPGA

2020 ◽  
Vol 13 (1) ◽  
pp. 91-98
Author(s):  
Ahmed K. Jameil ◽  
Yassir A. Ahmed ◽  
Saad Albawi
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
High Performance ◽  
Finite Impulse Response ◽  
Low Complexity ◽  
Fir Filter ◽  
Fir Filters ◽  
Filter Architecture ◽  
Circuit Techniques ◽  
And Performance

Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

scholarly journals A High-Performance FIR filter Architecture for Reconfigurable Applications

2019 ◽  
pp. 420-424
Author(s):  
R. Yerriswamy ◽  
D. Vishnu Vardhan ◽  
Sankar Lal Sharma
Keyword(s):  
High Performance ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Flow Diagram ◽  
Fir Filters ◽  
Significant Saving ◽  
Project Analysis ◽  
Complex Design ◽  
Direct Form ◽  
Filter Architecture

Transpose form finite-impulse response (FIR) filters are characteristically pipelined and support multiple constant multiplications (MCM) procedure that results in significant saving of calculation. However, transpose form configuration does not specifically support the block performing not like direct-form configuration. In this paper, we investigate the possibility of realization of block FIR filter in transpose shape configuration for area-delay efficient realization of huge order FIR filters for both fixed applications. Based on a detailed computational investigation of transpose form configuration of FIR filter, we have derived a flow diagram for transpose shape block FIR filter with reduced register complexity. A detailed block formulation is detailed for transpose form FIR filter. We have inferred a general multiplier-based architecture for the proposed transpose form block filter for reconfigurable applications. A reduced-complex design using multiple constant multiplications scheme is also showed for block implementation of fixed FIR filters. The proposed architecture obtains less area, less delay and less power consumption compared with the existing architecture of direct form structure for medium or long filter lengths. For this project analysis for determining area, power and delay it uses Xilinx.

An Ultra-Low Power Holter and Low Complexity Design Using Mixed Signal Processor

2013 ◽  
Vol 284-287 ◽  
pp. 1627-1632
Author(s):  
Hsieh Chang Huang ◽  
Ching Tang Hsieh ◽  
Guang Lin Hsieh
Keyword(s):  
Low Power ◽  
Analog Circuits ◽  
Finite Impulse Response ◽  
Low Complexity ◽  
Fir Filter ◽  
Ecg Signal ◽  
Ultra Low Power ◽  
Mixed Signal ◽  
Sd Card ◽  
Signal Processor

An ultra-low power, portable, and easily implemented Holter recorder is necessary for patients or researchers of electrocardiogram (ECG). Such a Holter recorder with off-the-shelf components is realized with mixed signal processor (MSP) in this paper. To decrease the complexity of analog circuits and the interference of 60 Hz noise from power line, we use the MSP to implement a finite impulse response (FIR) filter which is equiripple design. We also integrate the ring buffer for the input samples and the symmetrical characteristic of the FIR filter for efficiently computing convolution. The experimental results show that the ECG output signal with the PQRST feature is easy to be distinguished. This ECG signal is recorded for 24 hours using a SD card. Furthermore, the ECG signal is transmitted with a smartphone via Bluetooth to decrease the burden of the Holter recorder. As a result, this paper uses the Lomb method for the spectral analysis of Heart Rate Variability (HRV) better than Fast Fourier Transform (FFT).

scholarly journals DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS

2017 ◽  
Vol 10 (13) ◽  
pp. 66
Author(s):  
A Aparna ◽  
T Vigneswaran
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Research Work ◽  
Digital Signal ◽  
Fir Filter ◽  
Pass Filter ◽  
Finite Impulse Response Filters

This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications. 

scholarly journals Design and Accomplishment of Fir Filters for High Accuracy Reconfigurable Applications

2019 ◽  
Vol 8 (11S) ◽  
pp. 96-99
Keyword(s):  
Finite Impulse Response ◽  
Low Complexity ◽  
High Accuracy ◽  
Fir Filter ◽  
Fir Filters ◽  
Finite Impulse Response Filters ◽  
Filter Arrangement ◽  
Impulse Response Filters ◽  
Filter Area ◽  
Selection Of

The top function of the job is to establish transpose style Finite Impulse Response filters. That is pipelined along with furthermore constantly aids a variety of regular Entertainments come close to that cause conserving of calculation. Change kind of filter arrangement does say goodbye to straight support the block taking care of process. The MCM is instead much safer in Transpose variety when the normal operand is a couple of with the celebration of routine coefficients that diminish the computational hold-up. The execution of MCM approach is much less complicated out of commission coefficient Transpose design FIR filter however centre in reconfigurable coefficients. In arranged coefficients change FIR filter, area equally as great as hold-up is decreased by making use of MCM strategy. The low-complexity kind utilizing the MCM system is made an application for dealt with coefficients change design FIR filters like multiplier-established design is benefited from for reconfigurable transpose kind FIR filter. Critiques of the end results obtained guidance that efficiency metrics of the recommended execution is considerably harmonies with academic presumptions. Moreover, the recommended FPGA energy lies to include substantially so much less discipline-delay complexity on the other hand with the controlling DA-established implementations of FIR filter. For the actually the very same filter measurement similar to the similar block measurement, the advertised constitution needs thirteen% a lot less ADP as well as also 12.8% a lot less EPS than that of the present direct-from obstructs FIR structure. Based on these findings, we provide a scheme for the selection of direct-type and also transpose-kind company based on the filter dimensions and also block-length for obtaining subject-extend as well as furthermore power superior block FIR frameworks.

scholarly journals HIGH PERFORMANCE ADAPTIVE FINITE IMPULSE RESPONSE FILTER USING NEW DISTRIBUTED ARITHMETIC ALGORITHM

2017 ◽  
Vol 10 (13) ◽  
pp. 352
Author(s):  
Sandeep Kumar ◽  
Vigneswaran T
Keyword(s):  
Parallel Processing ◽  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Power Filter ◽  
Arithmetic Algorithm

Finite Impulse Response (FIR) filters is very important in signal Processing Applications. This research is to analyze the performance of FIR filter with the Xilinx Software. The Distributed Arithmetic (DA) algorithm is extensively used in FIR Filter to improve its speed and reducing the area of the filter. The design of low power filter will be achieved by pipelining and parallel processing concept on distributed Arithmetic. The aim is to design filter which has less delay time and supports the pipelining/parallel processing feature, helps in high speed with less power dissipation and area. The paper discusses FPGA implementation of FIR filter and due to parallel data processing its computation is fast and also provides an efficient architecture in terms of area and power consumption. New Distributed   Arithmetic is a high performance and for low power filter.

EFFICIENT RNS-BASED DESIGN OF PROGRAMMABLE FIR FILTERS TARGETING FPL TECHNOLOGY

2005 ◽  
Vol 14 (01) ◽  
pp. 165-177 ◽  
Author(s):  
JAVIER RAMÍREZ ◽  
UWE MEYER-BÄSE ◽  
ANTONIO GARCÍA
Keyword(s):  
High Performance ◽  
Digital Signal ◽  
Number System ◽  
Low Complexity ◽  
Residue Number System ◽  
Quadratic Residue ◽  
Fir Filter ◽  
Efficient Implementation ◽  
Fir Filters ◽  
Residue Number

FIR filters are routinely used in the implementation of modern digital signal processing systems. Their efficient implementation using commercially available VLSI technology is a subject of continuous study and development. This paper presents the residue number system (RNS) implementation of reduced-complexity and high-performance FIR filters, using modern Altera APEX20K field-programmable logic (FPL) devices. Index arithmetic over Galois fields and the Quadratic Residue Number System (QRNS), along with a selection of a small wordwidth modulus set, are the keys for attaining low complexity and high throughput in real and complex FIR filters. RNS–FPL merged FIR filters demonstrated its superiority when compared to 2C (two's complement) filters, being about 65% faster and requiring fewer logic elements for most study cases. Special attention was paid to an efficient implementation of the multi-operand modulo adders. The replacement of a classical modulo adder tree by a binary adder with extended precision followed by a single modulo reduction stage reduced area requirements by 10% for a 32-tap FIR filter. On the other hand, an index arithmetic QRNS-based complex FIR filter yielded up to 60% performance improvement over a three-multiplier-per-tap 2C filter, while requiring fewer LEs for filters having more than eight taps. Particularly, a 32-tap filter needed 24% LEs less than the classical design.

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

scholarly journals Constant-coefficient FIR filters based on residue number system arithmetic

2012 ◽  
Vol 9 (3) ◽  
pp. 325-342 ◽  
Author(s):  
Negovan Stamenkovic ◽  
Vladica Stojanovic
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Fir Filters ◽  
Residue Number ◽  
Low Power Dissipation ◽  
Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

scholarly journals A low complexity digital frequency calibration with high jitter immunity for ultra-low-power oscillators

2019 ◽  
Vol 17 ◽  
pp. 145-150
Author(s):  
Markus Scholl ◽  
Ralf Wunderlich ◽  
Stefan Heinen
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
Calibration Method ◽  
Low Complexity ◽  
Frequency Stability ◽  
Wireless Communication Systems ◽  
Ultra Low Power ◽  
Wireless Transceiver ◽  
Digital Frequency ◽  
Frequency Calibration

Abstract. This paper presents a highly efficient digital frequency calibration method for ultra-low-power oscillators in wireless communication systems. This calibration method locks the ultra-low-power oscillator's output frequency to the reference clock of the wireless transceiver during its send- and receive-state to achieve frequency stability over process variation and temperature drifts. The introduced calibration scheme offers high jitter immunity and short locking periods overcoming frequency calibration errors for typical ultra-low-power oscillator's by utilizing non-linear segmented feedback levels. In measurements the proposed calibration method improves the frequency stability of an ultra-low-power 32 kHz oscillator from 53 to 10 ppm ∘C−1 over a wide temperature range for temperature drifts of less than 1 ∘C s−1 with an estimated power consumption of 185 nW while coping with relocking periods of 7 ms.

Low Power Transposed Form 4-Tap Finite Impulse Response Filter using Power Efficient Multiply Accumulate Unit

2021 ◽  
pp. 2250016
Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
Speech Processing ◽  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Low Power Design ◽  
Fir Filter ◽  
Efficient Design ◽  
Power Efficient

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

Sign in / Sign up

Export Citation Format

Share Document