A fourth order bandpass delta-sigma A/D converter with input modulation network and digitally programmable passband

2002 ◽  
Author(s):  
Huining Liu ◽  
Xianggang Yu ◽  
T.L. Sculley ◽  
R.H. Bamberger
Keyword(s):  
Fourth Order ◽  
Delta Sigma ◽  
Digitally Programmable

A fourth-order bandwidth-reconfigurable delta—sigma modulator for audio applications

2012 ◽  
Vol 33 (7) ◽  
pp. 075002 ◽  
Author(s):  
Junqian Wang ◽  
Haifeng Yang ◽  
Rui Wei ◽  
Jun Xu ◽  
Junyan Ren
Keyword(s):  
Fourth Order ◽  
Delta Sigma Modulator ◽  
Delta Sigma

A 0.9-V 60-$\mu{\hbox {W}}$ 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range

2008 ◽  
Vol 43 (2) ◽  
pp. 361-370 ◽  
Author(s):  
Jeongjin Roh ◽  
Sanho Byun ◽  
Youngkil Choi ◽  
Hyungdong Roh ◽  
Yi-Gyeong Kim ◽  
...  
Keyword(s):  
Fourth Order ◽  
Dynamic Range ◽  
Delta Sigma Modulator ◽  
Delta Sigma

scholarly journals A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1093 ◽  
Author(s):  
Lee ◽  
Song ◽  
Roh
Keyword(s):  
High Resolution ◽  
Fourth Order ◽  
Power Efficiency ◽  
Dynamic Range ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Signal To Noise ◽  
Chopper Stabilization ◽  
Delta Sigma Modulator ◽  
Delta Sigma

This paper describes a fourth-order cascade-of-integrators with feedforward (CIFF) single-bit discrete-time (DT) switched-capacitor (SC) delta-sigma modulator (DSM) for high-resolution applications. This DSM is suitable for high-resolution applications at low frequency using a high-order modulator structure. The proposed operational transconductance amplifier (OTA), used a feedforward amplifier scheme that provided a high-power efficiency, a wider bandwidth, and a higher DC gain compared to recent designs. A chopper-stabilization technique was applied to the first integrator to remove the 1/f noise from the transistor, which is inversely proportional to the frequency. The designed DSM was implemented using 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The oversampling ratio (OSR) was 128, and the sampling frequency was 128 kHz. At a 500 Hz bandwidth, the signal-to-noise ratio (SNR) was 100.3 dB, the signal-to-noise distortion ratio (SNDR) was 98.5 dB, and the dynamic range (DR) was 103 dB. The measured total power dissipation was 99 µW from a 3.3 V supply voltage.

MULTI-STANDARD RECEIVER BASEBAND CHAIN USING DIGITALLY PROGRAMMABLE OTA BASED ON CCII AND CURRENT DIVISION NETWORKS

2013 ◽  
Vol 22 (04) ◽  
pp. 1350019 ◽  
Author(s):  
SOLIMAN A. MAHMOUD ◽  
EMAN A. SOLIMAN
Keyword(s):  
Power Consumption ◽  
Fourth Order ◽  
Second Generation ◽  
Cmos Technology ◽  
Current Conveyors ◽  
Baseband Receiver ◽  
Digitally Programmable ◽  
Dc Gain ◽  
Programmable Gain ◽  
Better Than

In this paper, a digitally programmable OTA-based multi-standard receiver baseband chain is presented. The multi-standard receiver baseband chain consists of two programmable gain amplifiers (PGA1 and PGA2) and a fourth-order LPF. The receiver is suitable for Bluetooth/UMTS/DVB-H/WLAN standards. Three different programmable OTA architectures based on second generation current conveyors (CCIIs) and Current Division Networks (CDNs) are discussed. The programmable OTA with the lowest power consumption, moderate area and good linearity — better than -50 dB HD3 — is selected to realize the multi-standard baseband receiver chain. The power consumption of the receiver chain is 6 mW. The DC gain varies over a 68 dB range with 1 MHz to 13.6 MHz programmable bandwidth. The receiver baseband chain is realized using 90 nm CMOS technology model under ±0.5 V voltage supply.

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