MULTI-STANDARD RECEIVER BASEBAND CHAIN USING DIGITALLY PROGRAMMABLE OTA BASED ON CCII AND CURRENT DIVISION NETWORKS

2013 ◽  
Vol 22 (04) ◽  
pp. 1350019 ◽  
Author(s):  
SOLIMAN A. MAHMOUD ◽  
EMAN A. SOLIMAN
Keyword(s):  
Power Consumption ◽  
Fourth Order ◽  
Second Generation ◽  
Cmos Technology ◽  
Current Conveyors ◽  
Baseband Receiver ◽  
Digitally Programmable ◽  
Dc Gain ◽  
Programmable Gain ◽  
Better Than

In this paper, a digitally programmable OTA-based multi-standard receiver baseband chain is presented. The multi-standard receiver baseband chain consists of two programmable gain amplifiers (PGA1 and PGA2) and a fourth-order LPF. The receiver is suitable for Bluetooth/UMTS/DVB-H/WLAN standards. Three different programmable OTA architectures based on second generation current conveyors (CCIIs) and Current Division Networks (CDNs) are discussed. The programmable OTA with the lowest power consumption, moderate area and good linearity — better than -50 dB HD3 — is selected to realize the multi-standard baseband receiver chain. The power consumption of the receiver chain is 6 mW. The DC gain varies over a 68 dB range with 1 MHz to 13.6 MHz programmable bandwidth. The receiver baseband chain is realized using 90 nm CMOS technology model under ±0.5 V voltage supply.

FULLY PROGRAMMABLE UNIVERSAL FILTER WITH INDEPENDENT GAIN-ω0-Q CONTROL BASED ON NEW DIGITALLY PROGRAMMABLE CMOS CCII

2009 ◽  
Vol 18 (05) ◽  
pp. 875-897 ◽  
Author(s):  
TAREK M. HASSAN ◽  
SOLIMAN A. MAHMOUD
Keyword(s):  
Cmos Technology ◽  
Code Word ◽  
Current Conveyor ◽  
Current Gain ◽  
Current Conveyors ◽  
High Current ◽  
Universal Filter ◽  
Output Stage ◽  
Class Ab ◽  
Digitally Programmable

A fully programmable second-order universal filter with independently controllable characteristics is presented in this paper. The proposed filter is based on a new ± 0.75 V second-generation current conveyor with digitally programmable current gain. The input stage of the current conveyor is realized using two complementary MOS differential pairs to ensure rail-to-rail operation. The output stage consists of a Class-AB CMOS push-pull network, which guarantees high current driving capability with a 47.2 μA standby current. The digital programmability of the current conveyor, based on transistor arrays and MOS switches, provides variable current gain using a digital code-word. Two approaches for implementing current conveyors with programmable current gain either greater or less than one are described. The fully programmable universal filter and the proposed digitally programmable current conveyor circuits are simulated using PSPICE with 0.25 μm CMOS technology from MOSIS.

A GAIN/FILTERING INTERLEAVED BASEBAND CHAIN ARCHITECTURES FOR MULTISTANDARD RECONFIGURABLE RECEIVERS

2012 ◽  
Vol 21 (01) ◽  
pp. 1250008 ◽  
Author(s):  
SOLIMAN A. MAHMOUD
Keyword(s):  
Supply Voltage ◽  
Intermediate Stage ◽  
Cmos Technology ◽  
System Level ◽  
A Value ◽  
Receiver Architecture ◽  
Dc Gain ◽  
Three Stages ◽  
Last Stage ◽  
Programmable Gain

In this paper, four baseband chain architectures used in multistandard (UMTS–WLAN) reconfigurable receivers will be introduced, simulated and, compared. The architectures are realized using 0.25 μm CMOS technology operating with 1.2 V supply voltage. The baseband chain consists of three stages: the first and the last stage are programmable gain amplifiers and the intermediate stage is an active Gm-RC LPF filter. The proposed architectures are compared in terms of DC-gain, noise, linearity, SFDR, and power consumption. The best receiver architecture is then derived based on system level analysis and based on a defined figure-of-merit. The best baseband chain bandwidth is controlled by the active Gm-RC filter with a value 2.2 MHz for UMTS and 11 MHz for WLAN. The baseband gain can be programmed in the range of -6÷68 dB, while the input-referred noise density is less 20 nV/√Hz for UMTS and 25 μV/√Hz for WLAN.

scholarly journals A Compact Size Wideband RF-VGA Based on Second Generation Controlled Current Conveyors

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1600
Author(s):  
J. del Pino ◽  
Sunil L. Khemchandani ◽  
D. Galante-Sempere ◽  
C. Luján-Martínez
Keyword(s):  
Power Consumption ◽  
Second Generation ◽  
Low Cost ◽  
Low Frequency ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Current Conveyors ◽  
Compact Size ◽  
Sige Bicmos ◽  
Controlled Current Conveyors

This paper presents a methodology to design a wideband radio frequency variable gain amplifier (RF-VGA) in a low-cost SiGe BiCMOS 0.35 μm process. The circuit uses two Class A amplifiers based on second-generation controlled current conveyors (CCCII). The main feature of this circuit is the wideband input match along with a reduced NF (5.5–9.6 dB) and, to the authors’ knowledge, the lowest die footprint reported (62 × 44 μm2 area). The implementation of the RF-VGA based on CCCII allows a wideband input match without the need of passive elements. Due to the nature of the circuit, when the gain is increased, the power consumption is reduced. The architecture is suitable for designing wideband, low-power, and low-noise amplifiers. The proposed design achieves a tunable gain of 6.7–18 dB and a power consumption of 1.7 mA with a ±1.5 V DC supply. At maximum gain, the proposed RF-VGA covers from DC up to 1 GHz and can find application in software design radios (SDRs), the low frequency medical implant communication system (MICS) or industrial, scientific, and medical (ISM) bands.

scholarly journals New Canonic Active RC Sinusoidal Oscillator Circuits Using Second-Generation Current Conveyors with Application as a Wide-Frequency Digitally Controlled Sinusoid Generator

2011 ◽  
Vol 2011 ◽  
pp. 1-8 ◽  
Author(s):  
Abhirup Lahiri
Keyword(s):  
Second Generation ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Variable Frequency ◽  
Current Conveyors ◽  
Frequency Range ◽  
Passive Components ◽  
Sinusoidal Oscillator ◽  
Digitally Controlled ◽  
Cmos Implementation

This paper reports two new circuit topologies using second-generation current conveyors (CCIIs) for realizing variable frequency sinusoidal oscillators with minimum passive components. The proposed topologies in this paper provide new realizations of resistance-controlled and capacitor-controlled variable frequency oscillators (VFOs) using only four passive components. The first topology employs three CCIIs, while the second topology employs two CCIIs. The second topology provides an advantageous feature of frequency tuning through two grounded elements. Application of the proposed circuits as a wide-frequency range digitally controlled sinusoid generator is exhibited wherein the digital frequency control has been enabled by replacing both the capacitors by two identical variable binary capacitor banks tunable by means of the same binary code. SPICE simulations of the CMOS implementation of the oscillators using 0.35 μm TSMC CMOS technology parameters and bipolar implementation of the oscillators using process parameters for NR200N-2X (NPN) and PR200N-2X (PNP) of bipolar arrays ALA400-CBIC-R have validated their workability. One of the oscillators (with CMOS implementation) is exemplified as a digitally controlled sinusoid generator with frequency generation from 25 kHz to 6.36 MHz, achieved by switching capacitors and with power consumption of 7 mW in the entire operating frequency range.

scholarly journals Low Cost Autonomous Lock-In Amplifier for Resistance/Capacitance Sensor Measurements

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1413 ◽  
Author(s):  
Paulina Maya ◽  
Belén Calvo ◽  
María Teresa Sanz-Pascual ◽  
Javier Osorio
Keyword(s):  
Phase Shifter ◽  
Low Cost ◽  
Cmos Technology ◽  
Signal Recovery ◽  
Automatic Phase ◽  
Digitally Programmable ◽  
Phase Alignment ◽  
Programmable Gain ◽  
On Chip ◽  
Lock In

This paper presents the design and experimental characterization of a portable high-precision single-phase lock-in instrument with phase adjustment. The core consists of an analog lock-in amplifier IC prototype, integrated in 0.18 µm CMOS technology with 1.8 V supply, which features programmable gain and operating frequency, resulting in a versatile on-chip solution with power consumption below 834 µW. It incorporates automatic phase alignment of the input and reference signals, performed through both a fixed −90° and a 4-bit digitally programmable phase shifter, specifically designed using commercially available components to operate at 1 kHz frequency. The system is driven by an Arduino YUN board, thus overall conforming a low-cost autonomous signal recovery instrument to determine, in real time, the electrical equivalent of resistive and capacitive sensors with a sensitivity of 16.3 µV/Ω @ εrS < 3% and 37 kV/F @ εrS < 5%, respectively.

Operational Amplifier Design Employing DTMOS Technique with Dual Supply Voltages

2021 ◽  
pp. 2250035
Author(s):  
Ersin Alaybeyoglu ◽  
Deniz Ozenli
Keyword(s):  
Power Consumption ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Portable Devices ◽  
Common Mode ◽  
The Core ◽  
Dc Gain ◽  
Supply Voltages ◽  
Amplifier Design

An operational amplifier (OPAMP) for portable devices with dual supply voltage is presented in this work. The design is realized with a 600[Formula: see text]mV supply for the core design and a 1.8[Formula: see text]V supply for the biasing circuit to improve input common mode range (ICMR), gain, and common mode rejection ratio (CMRR). The designed amplifier is implemented with dynamic threshold voltage MOSFET (DTMOS) transistors to decrease power consumption and increase the performance of the design. The power consumption of the core design is obtained as 2[Formula: see text][Formula: see text]W while the biasing circuitry consumes 7.38[Formula: see text][Formula: see text]W. The application of different supply voltages has greatly increased the gain of the circuit, where the circuit exhibits 100.2[Formula: see text]dB DC gain and 3.41[Formula: see text]MHz gain bandwidth product (GBW). CMRR of the designed circuit is 84.22[Formula: see text]dB. The simulations are performed in Cadence environment with 0.18[Formula: see text][Formula: see text]m CMOS technology.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

scholarly journals Static Switching Dynamic Buffer Circuit

2013 ◽  
Vol 2013 ◽  
pp. 1-11
Author(s):  
A. K. Pandey ◽  
R. A. Mishra ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Loading Condition ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Logic Function ◽  
Output Node ◽  
Switching Dynamic ◽  
Power Delay Product ◽  
Frequency Temperature

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

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