A Low Noise High Input Impedance Chopper-Stabilized Biopotential Amplifier with Ripple Reduction Technique

Biopotential signals are created as a result of the electrochemical activity of the many cells that comprise the nervous system, and they represent both normal and pathological organ function. These signals must be identified with extreme caution because they are surrounded by a great deal of noise when detected by sensors. This article explores a novel biopotential amplifier that incorporates the chopper stabilization technique to increase noise performance and minimize offset. However, by introducing the chopper modulator into the proposed design, the amplifier's overall input impedance was lowered, which was then increased to greater than 200 MΩ by adding the forward auxiliary path to the input branch. Additionally, the output ripple, produced due to switching activity and up-sampling, was reduced by inclusion of the R-C ripple removing block at the output of the operational transconductance amplifier (OTA). The designed architecture had a mid-band gain of 40dB with a power consumption of 9 µW and an offset of 10µV and a CMRR of 82 dB. It generated a noise of 42nV/√Hz. Also, the obtained results were compared with a conventional amplifier. The proposed design was verified by carrying out simulations using 180nm technology parameters. Cadence Virtuoso (Schematic editor), Spectre (Simulator), Symica and Magic (Layout) tools were used to complete the implementation and simulation of the proposed design. HIGHLIGHTS Biopotential signals are created as a result of the electrochemical activity of the many cells which must be identified with extreme caution because they are surrounded by a great deal of noise when detected by sensors It explores a novel biopotential amplifier that incorporates the chopper stabilization technique to increase noise performance and minimize offset By introducing the chopper modulator into the proposed design, the amplifier's overall input impedance was lowered, which was then increased to greater than 200 MΩ by adding the forward auxiliary path to the input branch The output ripple, produced due to switching activity and up-sampling, was reduced by inclusion of the R-C ripple removing block at the output of the operational transconductance amplifier (OTA) The designed architecture had a mid-band gain of 40dB with a power consumption of 9 µW and an offset of 10 µV and a CMRR of 82 dB. It generated a noise of 42 nV/√Hz GRAPHICAL ABSTRACT

A Potentiostat Readout Circuit with a Low-Noise and Mismatch-Tolerant Current Mirror Using Chopper Stabilization and Dynamic Element Matching for Electrochemical Sensors

This paper presents a potentiostat readout circuit with low-noise and mismatch-tolerant current mirror using chopper stabilization and dynamic element matching (DEM) for electrochemical sensors. Current-mode electrochemical sensors are widely used to detect the blood glucose and viruses in the diagnosis of various diseases such as diabetes, hyperlipidemia, and the H5N1 avian influenza virus (AIV). Low-noise and mismatch-tolerant characteristics are essential for sensing applications that require high reliability and high sensitivity. To achieve these characteristics, a proposed potentiostat readout circuit is implemented using the chopper stabilization scheme and the DEM technique. The proposed potentiostat readout circuit consists of a chopper-stabilized programmable gain transimpedance amplifier (TIA), gain-boosted cascode current mirror, and a control amplifier (CA). The chopper scheme, which is implemented in the TIA and CA, can reduce low frequency noise components, such as 1/f noise, and can obtain low-noise levels. The mismatch offsets of the cascode current mirror can be reduced by the DEM operation. The proposed current-mirror-based potentiostat readout circuit is designed using a standard 0.18 μm CMOS process and can measure the sensor current from 350 nA to 2.8 μA. The input-referred noise integrated from 0.1 Hz to 1 kHz is 21.7 pARMS, and the power consumption was 287.9 μW with a 1.8 V power supply.

A 5-nV/√Hz Chopper Negative-R Stabilization Preamplifier for Audio Applications

This paper presents a low-noise and low-power audio preamplifier. The proposed low-noise preamplifier employs a delay-time chopper stabilization (CHS) technique and a negative-R circuit, both in the auxiliary amplifier to cancel the non-idealities of the main amplifier. The proposed technique makes it possible to mitigate the preamplifier 1/f noise and thermal noise and improve its linearity. The low-noise preamplifier is implemented in 65 nm complementary metal-oxide semiconductor (CMOS) technology. The supply voltage is 1.2 V, while the power consumption is 159 µW, and the core area is 192 µm2. The proposed circuit of the preamplifier was fabricated and measured. From the measurement results over a signal bandwidth of 20 kHz, it achieves a signal-to-noise ratio (SNR) of 80 dB, an equivalent-input referred noise of 5 nV/√Hz and a noise efficiency factor (NEF) of 1.9 within the frequency range from 1 Hz to 20 kHz.

A Chopper Stabilization Audio Instrumentation Amplifier for IoT Applications

A low-noise instrumentation amplifier dedicated to a nano- and micro-electro-mechanical system (M&NEMS) microphone for the use in Internet of Things (IoT) applications is presented. The piezoresistive sensor and the electronic interface are respectively, silicon nanowires and an instrumentation amplifier. To design an instrumentation amplifier for IoT applications, different trade-offs are discussed like power consumption, gain, noise and sensitivity. Because the most critical noisy block is the amplifier, a delay-time chopper stabilization (CHS) technique is implemented around it to eliminate its offset and 1/f noise. The low-noise instrumentation amplifier is implemented in a 65-nm CMOS (Complementary metal–oxide–semiconductor) technology. The supply voltage is 2.5 V while the power consumption is 0.4 mW and the core area is 1 mm2. The circuit of the M&NEMS microphone and the amplifier was fabricated and measured. From measurement results over a signal bandwidth of 20 kHz, it achieves a signal-to-noise ratio (SNR) of 77 dB.

A 24.88 nV/√Hz Wheatstone Bridge Readout Integrated Circuit with Chopper-Stabilized Multipath Operational Amplifier

This paper proposes a low noise readout integrated circuit (IC) with a chopper-stabilized multipath operational amplifier suitable for a Wheatstone bridge sensor. The input voltage of the readout IC changes due to a change in input resistance, and is efficiently amplified using a three-operational amplifier instrumentation amplifier (IA) structure with high input impedance and adjustable gain. Furthermore, a chopper-stabilized multipath structure is applied to the operational amplifier, and a ripple reduction loop (RRL) in the low frequency path (LFP) is employed to attenuate the ripple generated by the chopper stabilization technique. A 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) is employed to convert the output voltage of the three-operational amplifier IA into digital code. The Wheatstone bridge readout IC is manufactured using a standard 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology, drawing 833 µA current from a 1.8 V supply. The input range and the input referred noise are ±20 mV and 24.88 nV/√Hz, respectively.

Low-Noise Multimodal Reconfigurable Sensor Readout Circuit for Voltage/Current/Resistive/Capacitive Microsensors

This paper presents a low-noise reconfigurable sensor readout circuit with a multimodal sensing chain for voltage/current/resistive/capacitive microsensors such that it can interface with a voltage, current, resistive, or capacitive microsensor, and can be reconfigured for a specific sensor application. The multimodal sensor readout circuit consists of a reconfigurable amplifier, programmable gain amplifier (PGA), low-pass filter (LPF), and analog-to-digital converter (ADC). A chopper stabilization technique was implemented in a multi-path operational amplifier to mitigate 1/f noise and offsets. The 1/f noise and offsets were up-converted by a chopper circuit and caused an output ripple. An AC-coupled ripple rejection loop (RRL) was implemented to reduce the output ripple caused by the chopper. When the amplifier was operated in the discrete-time mode, for example, the capacitive-sensing mode, a correlated double sampling (CDS) scheme reduced the low-frequency noise. The readout circuit was designed to use the 0.18-µm complementary metal-oxide-semiconductor (CMOS) process with an active area of 9.61 mm2. The total power consumption was 2.552 mW with a 1.8-V supply voltage. The measured input referred noise in the voltage-sensing mode was 5.25 µVrms from 1 Hz to 200 Hz.