A novel queuing architecture for background calibration of pipeline ADCs

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

10.1109/iscas.2004.1328132 ◽

2004 ◽

Author(s):

A. Savla ◽

J. Leonard ◽

A. Ravindran

Keyword(s):

Background Calibration ◽

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Digital architecture for background calibration of pipeline ADCs

5th IEE International Conference on ADDA 2005. Advanced A/D and D/A Conversion Techniques and their Applications ◽

10.1049/cp:20050171 ◽

2005 ◽

Author(s):

A. Delic-Ibukic

Keyword(s):

Background Calibration ◽

Digital Architecture ◽

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New swapping technique for background calibration of capacitor mismatch and amplifier finite DC-gain in pipeline ADCs

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-008-9195-4 ◽

2008 ◽

Vol 57 (1-2) ◽

pp. 57-68

Author(s):

Antonio J. Ginés ◽

Eduardo J. Peralías ◽

Adoración Rueda

Keyword(s):

Background Calibration ◽

Capacitor Mismatch ◽

Dc Gain ◽

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A research on the fast correlation-based background calibration techniques for the pipeline ADCs

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology ◽

10.1109/icsict.2010.5667685 ◽

2010 ◽

Author(s):

Shang-Quan Liang ◽

Yong-Sheng Yin ◽

Hong-Hui Deng ◽

Rui Zhang ◽

Jun Hu

Keyword(s):

Background Calibration ◽

Pipeline Adcs ◽

Calibration Techniques

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A mixed mode background calibration technique for pipeline ADCs

2009 4th IEEE Conference on Industrial Electronics and Applications ◽

10.1109/iciea.2009.5138643 ◽

2009 ◽

Author(s):

Jafar Sobhi ◽

Ziaeddin Kuzeh Kanani ◽

Ahamad Tahmasebi ◽

Mousa Yousefi

Keyword(s):

Background Calibration ◽

Calibration Technique ◽

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Background calibration of bit weights in pipeline ADCs using a counteracting dither technique

Electronics Letters ◽

10.1049/el.2020.0006 ◽

2020 ◽

Vol 56 (10) ◽

pp. 478-480

Author(s):

Jie Sun ◽

Yuan Zhou ◽

Xin Li

Keyword(s):

Background Calibration ◽

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Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2017.2718625 ◽

2017 ◽

Vol 25 (10) ◽

pp. 2966-2970 ◽

Author(s):

A. J. Gines ◽

E. J. Peralias ◽

A. Rueda

Keyword(s):

Background Calibration ◽

Pipeline Adcs ◽

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Digital background calibration technique for pipeline ADCs with multi-bit stages

16th Symposium on Integrated Circuits and Systems Design 2003 SBCCI 2003 Proceedings SBCCI-03 ◽

10.1109/sbcci.2003.1232847 ◽

2004 ◽

Author(s):

A.J. Gines ◽

E.J. Peralias ◽

A. Rueda

Keyword(s):

Background Calibration ◽

Calibration Technique ◽

Digital Background Calibration ◽

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Split ADC digital background calibration for high speed SHA-less pipeline ADCs

2014 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2014.6865342 ◽

2014 ◽

Author(s):

Hussein Adel ◽

Marc Sabut ◽

Roger Petigny ◽

Marie-Minerve Louerat

Keyword(s):

Background Calibration ◽

Digital Background Calibration ◽

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Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS

Proceedings of the 20th annual conference on Integrated circuits and systems design - SBCCI '07 ◽

10.1145/1284480.1284494 ◽

2007 ◽

Author(s):

Antonio J. Ginés ◽

Eduardo J. Peralías ◽

Adoración Rueda

Keyword(s):

Background Calibration ◽

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Digital Background Calibration for a 14-bit 100-MS/s Pipelined ADC Using Signal-Dependent Dithering

IEICE Transactions on Electronics ◽

10.1587/transele.e97.c.207 ◽

2014 ◽

Vol E97.C (3) ◽

pp. 207-214

Author(s):

Zhao-xin XIONG ◽

Min CAI ◽

Xiao-Yong HE ◽

Yun YANG

Keyword(s):

Pipelined Adc ◽

Background Calibration ◽

Digital Background Calibration

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