Global Interconnect Optimization in the Presence of On-chip Inductance

2007 ◽  
Author(s):  
Abinash Roy ◽  
Masud H. Chowdhury
Keyword(s):  
Interconnect Optimization ◽  
Global Interconnect ◽  
On Chip

scholarly journals Design optimization for capacitive-resistively driven on-chip global interconnect

2015 ◽  
Vol 12 (8) ◽  
pp. 20150111-20150111 ◽  
Author(s):  
Jianfei Jiang ◽  
Weifeng He ◽  
Jizeng Wei ◽  
Qin Wang ◽  
Zhigang Mao
Keyword(s):  
Design Optimization ◽  
Global Interconnect ◽  
On Chip

Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect

2008 ◽  
Vol 16 (6) ◽  
pp. 673-677 ◽  
Author(s):  
Prashant Singh ◽  
Jae-sun Seo ◽  
David Blaauw ◽  
Dennis Sylvester
Keyword(s):  
Low Power ◽  
High Speed ◽  
Global Interconnect ◽  
On Chip

scholarly journals Power-Estimation for On-Chip VLSI Distributed RLC Global Interconnect Using Model Order Reduction Technique

2010 ◽  
Vol 1 (14) ◽  
pp. 96-101 ◽  
Author(s):  
Rajib Kar ◽  
Vikas Maheshwari ◽  
Md. Maqbool ◽  
Ashis K. Mal ◽  
A.K. Bhattacharjee
Keyword(s):  
Model Order Reduction ◽  
Order Reduction ◽  
Power Estimation ◽  
Reduction Technique ◽  
Model Order ◽  
Global Interconnect ◽  
On Chip

On-chip Interconnect Optimization and Validation using Virtual Platform

2020 ◽  
Author(s):  
Jungyun Choi ◽  
Kyungsu Kang ◽  
Sangho Park ◽  
Seunghan Lee ◽  
Yohan Park ◽  
...  
Keyword(s):  
Interconnect Optimization ◽  
Virtual Platform ◽  
On Chip
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