global interconnect Latest Research Papers

Air-Gap Technology With a Large Void-Fraction for Global Interconnect Delay Reduction

IEEE Transactions on Electron Devices ◽

10.1109/ted.2021.3105086 ◽

2021 ◽

pp. 1-7

Author(s):

Clarissa Prawoto ◽

Zichao Ma ◽

Ying Xiao ◽

Salahuddin Raju ◽

Mansun Chan

Keyword(s):

Void Fraction ◽

Air Gap ◽

Delay Reduction ◽

Large Void ◽

Interconnect Delay ◽

Global Interconnect ◽

Gap Technology

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25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range

2020 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc19947.2020.9063158 ◽

2020 ◽

Author(s):

Mark A. Anders ◽

Himanshu Kaul ◽

Seongjong Kim ◽

Gregory K. Chen ◽

Raghavan Kumar ◽

...

Keyword(s):

High Performance ◽

Current Mode ◽

Transient Current ◽

Operating Range ◽

Voltage Frequency ◽

Global Interconnect ◽

Interconnect Circuits

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The Global Interconnect Routing Approach for Reconfigurable System-on-a-Chip

2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) ◽

10.1109/eiconrus49466.2020.9039182 ◽

2020 ◽

Author(s):

Mariya A. Zapletina ◽

Daniil A. Zheleznikov ◽

Sergey V. Gavrilov

Keyword(s):

Reconfigurable System ◽

System On A Chip ◽

Global Interconnect ◽

Interconnect Routing

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Global Interconnect Optimization

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) ◽

10.1109/iccad45719.2019.8942155 ◽

2019 ◽

Author(s):

Siad Daboul ◽

Stephan Held ◽

Bento Natura ◽

Daniel Rotter

Keyword(s):

Interconnect Optimization ◽

Global Interconnect

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Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing

Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19 ◽

10.1145/3299874.3319491 ◽

2019 ◽

Cited By ~ 2

Author(s):

Adarsha Balaji ◽

Yuefeng Wu ◽

Anup Das ◽

Francky Catthoor ◽

Siebren Schaafsma

Keyword(s):

Neuromorphic Computing ◽

Global Interconnect

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Capacitively Driven Global Interconnect With Energy-Efficient Receiver Based on Magneto-Electric Switching

IEEE Magnetics Letters ◽

10.1109/lmag.2018.2826460 ◽

2018 ◽

Vol 9 ◽

pp. 1-5

Author(s):

Zubair Al Azim ◽

Akhilesh Jaiswal ◽

Indranil Chakraborty ◽

Kaushik Roy

Keyword(s):

Energy Efficient ◽

Global Interconnect

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Transmission line model for inherently stable MSWCNT bundled global interconnect for 22nm technology node

2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON) ◽

10.1109/upcon.2017.8251044 ◽

2017 ◽

Author(s):

Shailendra Mishra ◽

Divya Mishra

Keyword(s):

Transmission Line ◽

Transmission Line Model ◽

Line Model ◽

Technology Node ◽

Global Interconnect

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Design optimization for AC coupled on-chip global interconnect

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict.2016.7998789 ◽

2016 ◽

Author(s):

Jianfei Jiang ◽

Qin Wang ◽

Weifeng He ◽

Xiaoyang Zeng

Keyword(s):

Design Optimization ◽

Global Interconnect ◽

On Chip

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A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis

Journal of Electronic Testing ◽

10.1007/s10836-015-5515-7 ◽

2015 ◽

Vol 31 (2) ◽

pp. 207-215 ◽

Cited By ~ 9

Author(s):

Igor Gadelha Pereira ◽

Leonardo Alves Dias ◽

Cleonilson Protásio de Souza

Keyword(s):

Shift Register ◽

Interconnect Testing ◽

Global Interconnect

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Design optimization for capacitive-resistively driven on-chip global interconnect

IEICE Electronics Express ◽

10.1587/elex.12.20150111 ◽

2015 ◽

Vol 12 (8) ◽

pp. 20150111-20150111 ◽

Cited By ~ 1

Author(s):

Jianfei Jiang ◽

Weifeng He ◽

Jizeng Wei ◽

Qin Wang ◽

Zhigang Mao

Keyword(s):

Design Optimization ◽

Global Interconnect ◽

On Chip

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global interconnect
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

Air-Gap Technology With a Large Void-Fraction for Global Interconnect Delay Reduction

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range

The Global Interconnect Routing Approach for Reconfigurable System-on-a-Chip

Global Interconnect Optimization

Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing

Capacitively Driven Global Interconnect With Energy-Efficient Receiver Based on Magneto-Electric Switching

Transmission line model for inherently stable MSWCNT bundled global interconnect for 22nm technology node

Design optimization for AC coupled on-chip global interconnect

A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis

Design optimization for capacitive-resistively driven on-chip global interconnect

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global interconnectRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

Air-Gap Technology With a Large Void-Fraction for Global Interconnect Delay Reduction

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range

The Global Interconnect Routing Approach for Reconfigurable System-on-a-Chip

Global Interconnect Optimization

Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing

Capacitively Driven Global Interconnect With Energy-Efficient Receiver Based on Magneto-Electric Switching

Transmission line model for inherently stable MSWCNT bundled global interconnect for 22nm technology node

Design optimization for AC coupled on-chip global interconnect

A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis

Design optimization for capacitive-resistively driven on-chip global interconnect

global interconnect
Recently Published Documents