A practical hardware design for the keypoint detection in the SIFT algorithm with a reduced memory requirement

2012 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2012.6272152 ◽

2012 ◽

Author(s):

Eung Sup Kim ◽

Hyuk-Jae Lee

Keyword(s):

Hardware Design ◽

Memory Requirement ◽

Sift Algorithm ◽

Keypoint Detection

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A novel hardware design for SIFT generation with reduced memory requirement

JSTS Journal of Semiconductor Technology and Science ◽

10.5573/jsts.2013.13.2.157 ◽

2013 ◽

Vol 13 (2) ◽

pp. 157-169 ◽

Author(s):

Eung Sup Kim ◽

Hyuk-Jae Lee

Keyword(s):

Hardware Design ◽

Memory Requirement

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Hardware Design of Feature Point Extraction using SIFT algorithm

10.14257/astl.2014.48.08 ◽

2014 ◽

Author(s):

Gi-woong Shin ◽

Jong-tae Sung ◽

Young-Hyoung Kim

Keyword(s):

Hardware Design ◽

Feature Point ◽

Sift Algorithm ◽

Feature Point Extraction

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ASP-SIFT: Using Analog Signal Processing Architecture to Accelerate Keypoint Detection of SIFT Algorithm

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2019.2936818 ◽

2020 ◽

Vol 28 (1) ◽

pp. 198-211

Author(s):

Zichen Fan ◽

Zheyu Liu ◽

Zheng Qu ◽

Fei Qiao ◽

Qi Wei ◽

...

Keyword(s):

Signal Processing ◽

Analog Signal Processing ◽

Analog Signal ◽

Sift Algorithm ◽

Keypoint Detection ◽

Processing Architecture

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An efficient hardware design of SIFT algorithm using fault tolerant reversible logic

2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS) ◽

10.1109/retis.2015.7232933 ◽

2015 ◽

Author(s):

Chandrajit Pal ◽

Pabitra Das ◽

Sudhindu Bikash Mandal ◽

Amlan Chakrabarti ◽

Samik Basu ◽

...

Keyword(s):

Fault Tolerant ◽

Hardware Design ◽

Reversible Logic ◽

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Parallelization of Computing-Intensive Tasks of SIFT Algorithm on a Reconfigurable Architecture System

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e96.a.1393 ◽

2013 ◽

Vol E96.A (6) ◽

pp. 1393-1402 ◽

Author(s):

Peng OUYANG ◽

Shouyi YIN ◽

Hui GAO ◽

Leibo LIU ◽

Shaojun WEI

Keyword(s):

Reconfigurable Architecture ◽

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Memory Requirement Reduction of Deep Neural Networks for Field Programmable Gate Arrays Using Low-Bit Quantization of Parameters

2020 28th European Signal Processing Conference (EUSIPCO) ◽

10.23919/eusipco47968.2020.9287739 ◽

2021 ◽

Author(s):

Niccolo Nicodemo ◽

Gaurav Naithani ◽

Konstantinos Drossos ◽

Tuomas Virtanen ◽

Roberto Saletti

Keyword(s):

Neural Networks ◽

Deep Neural Networks ◽

Field Programmable Gate Arrays ◽

Memory Requirement ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

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VLSI Based Low Power Hardware Design Using Distributed Arithmetic (DA) Centered 2d Adam7 Transform For The Proposed Image Compression Algorithm

i-manager’s Journal on Embedded Systems ◽

10.26634/jes.2.2.2374 ◽

2013 ◽

Vol 2 (2) ◽

pp. 31-37

Author(s):

L. Vignesh ◽

◽

C. N. Marimuthu ◽

J. Joseph Lynn ◽

◽

...

Keyword(s):

Image Compression ◽

Low Power ◽

Hardware Design ◽

Compression Algorithm ◽

Distributed Arithmetic ◽

Image Compression Algorithm

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Standard for SystemVerilog. Unified hardware design, specification and verification language

10.3403/30167898u ◽

2015 ◽

Keyword(s):

Hardware Design ◽

Design Specification ◽

Specification And Verification

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Nuclear power plants. Instrumentation and control important to safety. Hardware design requirements for computer-based systems

10.3403/30186286 ◽

2009 ◽

Keyword(s):

Nuclear Power ◽

Power Plants ◽

Nuclear Power Plants ◽

Hardware Design ◽

Computer Based ◽

Design Requirements ◽

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Nuclear power plants. Instrumentation and control important to safety. Hardware design requirements for computer-based systems

10.3403/30299629 ◽

2015 ◽

Keyword(s):

Nuclear Power ◽

Power Plants ◽

Nuclear Power Plants ◽

Hardware Design ◽

Computer Based ◽

Design Requirements ◽

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