scholarly journals Extracting Weak PUFs from Differential Nonlinearity of Digital-to-Analog Converters

Author(s):  
Andreas Herkle ◽  
Holger Mandry ◽  
Stefan Reich ◽  
Markus Sporer ◽  
Joachim Becker ◽  
...  
Author(s):  
Sang-Hee Yoon ◽  
Young-Ho Cho

This paper presents 4-digit digital microflow controllers where fluidic digital-to-analog converters (DACs) achieve an improved linearity with finer flow-rate levels for a given number of digital valves. The fluidic DAC, composed of microchannels with binary-weighted flow resistors, controls flow-rate levels not based on the magnitude of flow resistances, but based on the ratio of the flow resistance. We deign the flow resistance of microchannel using a serial or a parallel connection of an identical fluidic resistor, thus making the controllable flow-rates insensitive to the micromachining errors. Prototype S and P with serial and parallel connections of a unit fluidic resistor and prototype V with the fluidic resistors having different channel width are fabricated using micromachining. At a constant pressure of 2kPa, prototypes S, P and V show the maximum error of 7.5%, 6.2% and 22.5% in the flow-rate range of 0.09μ1/s to 3.33μ1/s, resulting in the differential nonlinearity of 0.28, 0.27 and 0.94, respectively. The prototypes S and P show 70.2% and 71.2% less sensitive to micromachining errors than prototype V, respectively.


2011 ◽  
Vol 70 (2) ◽  
pp. 159-169
Author(s):  
A. N. Rudyakova ◽  
A. Yu. Lipinsky ◽  
V. V. Danilov

2021 ◽  
Vol 2 (2) ◽  
pp. 2170004
Author(s):  
Jiawei Meng ◽  
Mario Miscuglio ◽  
Jonathan K. George ◽  
Aydin Babakhani ◽  
Volker J. Sorger

2017 ◽  
Vol 2017 ◽  
pp. 1-10
Author(s):  
Jinpeng Qiu ◽  
Tong Liu ◽  
Xubin Chen ◽  
Yongheng Shang ◽  
Jiongjiong Mo ◽  
...  

This paper presents a new 12-bit digital to analog converter (DAC) circuit based on a low-offset bandgap reference (BGR) circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an accuracy DAC output signal to the buffer operational amplifier. The proposed circuit was fabricated in CSMC 0.5 μm 5 V 1P4M process. The measured differential nonlinearity (DNL) of the output voltages is less than 0.45 LSB and integral nonlinearity (INL) less than 1.5 LSB at room temperature, consuming only 3.5 mW from a 5 V supply voltage. The DNL and INL at −55°C and 125°C are presented as well together with the discussion of possibility of improving the DNL and INL accuracy in future design.


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