Design of a 9-bit column-parallel ADC in the MAPS for real-time beam monitoring

This paper describes a 2 Msps 9-bit column-parallel ADC for monolithic active pixel sensor. It is designed in fully differential cyclic architecture and takes eight clock cycles to perform a 9-bit conversion. This ADC is fabricated in a 130 nm CMOS process. Each ADC covers a small area of 100 µm × 300 µm and consumes ∼5 mW. The measurement results show that this ADC has a signal-to-noise and distortion ratio (SNDR) of 46.8 dB. The DNL (Differential Nonlinearity) and (Integral Nonlinearity) INL are 0.168 LSB and 0.112 LSB, respectively. The effective number of bits (ENOB) is 7.48 bits.

A New Structure of 8-Bit 60 MS/s SAR-ADC Using a Reduced Switching Capacitor-DAC Array

This paper presents an analysis of the Reduced Switching Capacitor Digital-to-Analog Converter (RSC-DAC)-based low power Successive Approximation Register Analog to Digital Converter (SAR-ADC). The proposed structure involves the Low voltage Static D-Latch Comparator (LSD-LC) with pre-amplifier operators in two modes (Normal and Hold), the RSC-DAC switching energy, reduced by 93% contrast to the standard Charge Redistribution Switching Capacitor DAC (CRSC-DAC) method, and the Successive Approximation Register (SAR) control logic. The LSD-LC with pre-amplifier consists of a latch circuit and a pre-amplifier. The pre-amplifier is often used to eliminate the DC offset voltage and kickback noise without substantially weakening the Signal-to-Noise Ratio (SNR) to drive the main circuit while the latch is needed for comparison. The linearity parameters such as Integral Nonlinearity, Differential Nonlinearity and effect of parasitic capacitances of the RSC-DAC are analyzed and improved by the new approach named as Adaptive Random Code Generation (ARCG) Technique. The above overall design is implemented in 250-nm CMOS design of the TANNER-EDA tool, consuming 1.74-mW power at 60[Formula: see text]MS/s. The proposed structure has an INL and a DNL, respectively, of +0.18/[Formula: see text] LSB and +0.11/[Formula: see text]0.05 LSB.

METHOD FOR NONLINEARITY MINIMIZATION OF MULTIPLYING DIGITAL-TO-ANALOG CONVERTER BY LOW RESOLUTION CALIBRATION CONVERTER

Представлен метод минимизации нелинейности передаточной характеристики прецизионного умножающего цифро-аналогового преобразователя (ЦАП) с помощью вспомогательного корректирующего ЦАП малой разрядности. В данном методе вспомогательный ЦАП формирует искаженную передаточную характеристику, которая в сумме с передаточной характеристикой основного ЦАП позволяет уменьшить результирующую интегральную и дифференциальную нелинейность. Коэффициенты коррекции, рассчитанные согласно представленному в статье алгоритму, однократно записываются в энергонезависимую память и преобразуются в управляющий сигнал для калибрующего ЦАП с помощью арифметико-логического устройства (АЛУ) в зависимости от входных данных. Для проведения экспериментальных исследований был разработан макет системы калибровки на основе программируемой логической интегральной схемы (ПЛИС) и демонстрационной платы с микросхемой двухканального 16-разрядного ЦАП с сегментированной структурой. Представлены экспериментальные результаты, которые показывают, что в данной системе коррекции собственная нелинейность калибрующего ЦАП не оказывает существенного влияния на итоговую передаточную характеристику. Приведенный алгоритм расчета коэффициентов позволяет эффективно уменьшить абсолютную интегральную и дифференциальную нелинейность 16-разрядного ЦАП до значений менее 1 единицы веса младшего разряда (ЕМР) In this paper, we present a method for nonlinearity minimization of precision multiplying digital-to-analog converter (DAC) by utilizing low resolution calibration DAC. In this method the calibration DAC generates distorted transfer characteristic which is added to the main DAC characteristic and provides resulting integral and differential nonlinearity reduction. The calibration coefficients are calculated following the presented algorithm and saved in nonvolatile memory and then are converted to controlling digital code of calibration DAC by arithmetical-logical unit (ALU) depending on input data. For experimental research we designed a model of calibration system based on field programmable gate array (FPGA) and a demo board with dual 16-bit segmented DAC. Then we give experimental results which show that inherent nonlinearity of calibration DAC does not significantly affect overall nonlinearity. The proposed calculation algorithm obtains effective integral and differential nonlinearity minimization of 16-bit DAC down to values of less than one least significant bit (LSB)

Analysis of Reversible Switching Capacitive DAC Based Low Power SAR-ADC

This paper presents an analysis of Reversible Switching Capacitive Digital to Analog converter (RSC-DAC) based low power Successive Approximation Register Analog to Digital Converter (SAR-ADC).The proposed structure involves, the QVDC (Quantum Voltage Differential Comparator) constructed using Simple Transconductance Amplifier (STA) technique , the RSC-DAC switching energy reduced by 93% contrast to the standard Charge Redistribution Switching Capacitive DAC (CRSC-DAC) method, and the Successive Approximation Register(SAR) control logic is designed with D-FF based shift register. The QVDC comparator allows very small voltage comparison, and consumes low power and area effective. The linearity parameters such as Integral Nonlinearity, Differential Nonlinearity and parasitic effect of the capacitor of the RSC-DAC is analyzed and improved by the new approach is named as Adaptive Random Code Generation (ARCG) Technique. The above overall design is implemented by TANNER-EDA tool in 250nm CMOS technology, consumes 1.74mW power at 60MS/s. The INL and DNL of the proposed structure is +0.18/-0.12 LSB and +0.11/-0.05 LSB respectively.

A 4-bit 36 GS/s ADC with 18 GHz Analog Bandwidth in 40 nm CMOS Process

This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eight time-interleaved (TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS) process. A wideband front-end matching circuit based on a peaking inductor is designed to increase the analog input bandwidth to 18 GHz. A novel offset calibration that can achieve quick detection and accurate correction without affecting the speed of the comparator is proposed, guaranteeing the high-speed operation of the ADC. A clock distribution circuit based on CMOS and current mode logic (CML) is implemented in the proposed ADC, which not only maintains the speed and quality of the high-speed clock, but also reduces the overall power consumption. A timing mismatch calibration is integrated into the chip to achieve fast timing mismatch detection of the input signal which is bandlimited to the Nyquist frequency for the complete ADC system. The experimental results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.28/+0.22 least significant bit (LSB) and −0.19/+0.16 LSB, respectively. The signal-to-noise-and-distortion ratio (SNDR) is above 22.5 dB and the spurious free dynamic range (SFDR) is better than 35 dB at 1.2 GHz. An SFDR above 24.5 dB and an SNDR above 18.6 dB across the entire Nyquist frequency can be achieved. With a die size of 2.96 mm * 1.8 mm, the ADC consumes 780 mW from the 0.9/1.2/1.8 V power supply.

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation.

Different Analog to Digital Converters Architectures

A series of recent studies has indicated that a mixed signal device analog to digital converters used for the processing of information and play a vital role in wireless sensors, Digital signal processing, Biomedical devices, in communication, IOT and various other applications. Across this broad use they give the significance in designing. The paper represents the various parameters like speed, area occupied, power consumption, sampling Rate, precision, Signal to noise ratio, Signal to noise distortion ratio, resolution, linearity and conversion time with respect to its different types and broad application in the real world. It defines errors due to non – linearity of signals as Differential nonlinearity, Integral nonlinearity, gain error, quantization error, aliasing and offset error. It also gives the comparative study about ADCs.

An Area-Efficient 10-Bit Buffer-Reused DAC for AMOLED Column Driver ICs

In this paper, we proposed an area-efficient 10-bit digital-to-analog converter (DAC) with buffer-reusing method to dramatically relief the severe area exploding issue in high-definition active-matrix organic light-emitting diode (AMOLED) driver integrated circuits (ICs). In our design, we implement the functionalities of a large number of switches and capacitors in conventional DAC by a compact internal buffer. Furthermore, we minimize the buffer capacity requirement by elaborately reusing the indispensable output buffer in the typical column driver. In this way, we can cut down nearly a half of the decoder-switches and simultaneously reduce the capacitor size from 8 C to 3 C without designing an intricate and power-consuming amplifier separately. A prototype 6-channel column driver employing the proposed buffer-reused DAC was fabricated by 0.35 μm 2P3M BCD (Bipolar, CMOS, DMOS) process and its effective layout area per channel is 0.0429 mm2, which is 42.8% smaller than that of the conventional 10-bit R-C DAC. Besides, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.514 LSB/0.631 LSB, respectively and the maximum value of inter-channel deviation voltage output (DVO) is 3.25 mV. The settling time within 5.6 μs is readily achieved under 1.5 kΩ-resistance and 100 pF-capacitance load. Measurement results indicate that the proposed buffer-reused DAC can successfully minimize the die area while maintaining other required performances.

Current Measurement Transducer Based on Current-To-Voltage-To-Frequency Converting Ring Oscillator with Cascade Bias Circuit

We propose a ring oscillator (RO) based current-to-voltage-to-frequency (I–V–F) converting current transducer with a cascade bias circuit. The I–V–F converting scheme guarantees highly stable biasing against RO, with a rail-to-rail output operation. This device was fabricated using National NanoFab Center (NNFC) 180 nm complementary metal-oxide-semiconductor (CMOS) technology, which achieves a current resolution of 1 nA in a measurement range up to 200 nA. A noise floor of 11.8 pA/√Hz, maximum differential nonlinearity (DNL) of 0.15 in 1 nA steps, and rail-to-rail output with a 1.8 V power supply is achieved. The proposed transducer can be effectively applied to bio-sensing devices requiring a compact area and low power consumption with a low current output. The fabricated structure can be applied to monolithic-three-dimensional integration with a bio-sensing device.