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2021 ◽  
Author(s):  
Emad AbdelAziz Mohamed ◽  
Henry Ewart Edwards

Analogue outcrops can be used to prepare geoscientists with realistic expectations and responses for Geosteering ultra-long horizontal wells (ERD) in thin reservoirs with different scales of faults, and uncertainty in fault zone parameters and characteristics. Geosteering ultra-long horizontal wells in specific, thin, meter-thick target zones within reservoirs is challenged when sub-seismic faults are present or where seismic scale fault throw and fault location is ill-defined or imprecisely known. This paper defines the challenge of how analogue outcrops can be used to prepare geoscientists with realistic expectations and responses to such operational difficulties in faulted carbonates, irrespective of the tools employed to characterize encountered faults. Geosteering wells in reservoirs with different scales of faults and uncertainty in fault zone character and detection limits can lead to: (i) extensive ‘out of zone’ intervals and (ii) undulating wellbores (when attempting to retrieve target layer positioning), whereby well productivity and accessibility are compromised. Using faulted carbonate field analogues can direct the operation geologist's geosteering response to such faulted scenarios. Descriptions from outcrops are used to address subsurface scenarios of marker horizon(s) and their lateral/spatial variability; diagenesis related to faults at outcrop and expected variations along wellbore laterals in the oilfield. Additionally, offsets/throws, damage zone geometries for thin-bed reservoir understanding of fault zone effects in low-offset structures. Appreciation of faults in outcrops allows an understanding of expectations whilst drilling according to the following: (1) Scales of features from seismic to sub-seismic damage zones: what to expect when geosteering within / out of zone, across faults with indeterminate throws. (2) Understandings from 3D analogues/geometries applied predictively to field development, targeting specific thin reservoir zones / key marker beds. Several oil- well case-examples highlight the response in steering wellbores located within specific thin target zones whereby faults were expected, but where fault throw differed significantly to what was anticipated from initial seismic interpretation. Examples elucidating the application include a meter-thick dolomite zone within a very thick limestone reservoir where injector and producer wells are completed, where the wellbore remains within reservoir but out of specific target zone (how to marry smooth wellbore with layer conformance). Furthermore, for very thin reservoirs primarily located within non-reservoir carbonates, minor faults would misdirect wellbore into argillaceous limestone above or below the reservoirs. Faulted zones with water influx mapped from LWD where modelled property responses can be better characterized by low-offset faults with compartmentalizing effects for completion strategies. Even with an extensive suite of logs to characterize fault zones, the objective of Geosteering a well continuously within zone becomes difficult. Selected key tools are required for success. Directly using Early Cretaceous reservoir analogues, with specific fault types and displacements, critically aid geosteering practices for QA, prediction and learnings.


2021 ◽  
Author(s):  
Ara Abdulsatar Assim Assim ◽  
Evgenii Balashov

The given work is devoted to designing and implementing different dynamic offset cancellation techniques for 50 nm technology CMOS operational amplifiers. The goal is to minimize or get rid of the effects of the offset voltage. Offset voltage exists in all differential amplifiers due to the fact that no pair of transistors can be fabricated with the same size, there is always a slight difference in their dimensions (length or width), this gives rise to an undesirable effect called offset, the value of offset voltage for cheap commercial amplifiers are in the range of 1 to 10 mV, de-spite the fact that this isn’t a significant value, due to the high gain of such amplifiers, this voltage is amplified by tens or hundreds of times, this results in clipping of the output signal and this further limits the amplifier’s maximum allowable input voltage within the given dynamic range, hence its of great importance to take this small voltage into consideration, low-offset amplifiers find applications in mixers, analog to digital converters, instrumentation devices, etc. In this thesis, by using two different techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational amplifiers were designed. The implemented methods reduced the flicker noise by more than 457 times (from 9.4 nV/√Hz to 20 pV/√Hz) at 1 Hz. All the simulations were done using Cadence Virtuoso.


2021 ◽  
Author(s):  
Ara Abdulsatar Assim Assim ◽  
Evgenii Balashov

The given work is devoted to designing and implementing different dynamic offset cancellation techniques for 50 nm technology CMOS operational amplifiers. The goal is to minimize or get rid of the effects of the offset voltage. Offset voltage exists in all differential amplifiers due to the fact that no pair of transistors can be fabricated with the same size, there is always a slight difference in their dimensions (length or width), this gives rise to an undesirable effect called offset, the value of offset voltage for cheap commercial amplifiers are in the range of 1 to 10 mV, de-spite the fact that this isn’t a significant value, due to the high gain of such amplifiers, this voltage is amplified by tens or hundreds of times, this results in clipping of the output signal and this further limits the amplifier’s maximum allowable input voltage within the given dynamic range, hence its of great importance to take this small voltage into consideration, low-offset amplifiers find applications in mixers, analog to digital converters, instrumentation devices, etc. In this thesis, by using two different techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational amplifiers were designed. The implemented methods reduced the flicker noise by more than 457 times (from 9.4 nV/√Hz to 20 pV/√Hz) at 1 Hz. All the simulations were done using Cadence Virtuoso.


2021 ◽  
Author(s):  
Bing Yuan ◽  
Langqi Xiao ◽  
Jing Ying ◽  
Bingyuan Wang
Keyword(s):  

Author(s):  
Hua Fan ◽  
Peng Lei ◽  
Jingxuan Yang ◽  
Quanyuan Feng ◽  
Qi Wei ◽  
...  

Author(s):  
Eka Fitrah Pribadi ◽  
Rajeev Kumar Pandey ◽  
Paul C.-P. Chao

Abstract A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.


Author(s):  
Jeffin Joy ◽  
Swetha Clara Jose ◽  
Vijaya Kumar Kanchetla ◽  
Shubham Jain ◽  
Rajesh Zele
Keyword(s):  

Author(s):  
Posani Vijaya Lakshmi ◽  
Sarada Musala ◽  
Avireni Srinivasulu

Aims: To propose an 8-bit differential input low power successive approximation register (SAR) ADC with digital error correction technique for sensing bio-potential signals in wearable and implantable devices. Background: As Dynamic comparators have the advantages of full swing output, low power consumption, high speed, and high impedance at the input, they are preferably used in energy efficient SAR ADC’s. But since dynamic comparator is the most frequently used block in SAR ADC, research is ongoing to furthermore reduce its µW power. Also, as offset voltage of comparator affects the linearity of ADC, it must be minimized. Linearity can further be improved by calibrating the output of ADC and extensive survey on the calibration methods prove that addition only digital error correction method is efficient in terms of power. Objective: To design a low power and low offset dynamic comparator intended for SAR ADC to achieve highly linear digital output. In addition to this, to implement a power efficient digital error correction technique for the output of SAR ADC to overcome the non-idealities due to process variations. Method: As power consumption is proportional to the number of transistors, proposed comparator is a design obtaining same output as the existing dynamic comparators with reduced transistor count. The proposed comparator along with low power full swing three input XOR logic gate is implemented in SAR ADC with digital error correction technique in cadence 45 nm technology files and its performance parameters are simulated. Result: The layout of the proposed dynamic comparator occupies an area of 3 µm2. The simulation results of this comparator with a load of 1 pF show that it has a total offset of 11.2 mV, delay of 0.9 ns and power consumption of 24 nW. It also achieves a gain of 49.5 i.e 33.86 dB. The 8-bit ADC along with digital error correction technique operating at 143-kS/s and under 0.6 V supply voltage simulated in 45nm technology consumes only 0.12 µW power. The DNL and INL error obtained are +0.22/-0.2 LSB and -0.28 LSB respectively. SNR limited by noise is 48.25 dB, SFDR is 48.64 dB and ENOB achieved is 7.72. Conclusion: To satisfy the requirement of the wearable and implantable devices a low power SAR ADC with good linearity is designed using low power and low offset dynamic comparator. A digital error correction technique using low power XOR logic gate is implemented at the SAR ADC output to minimize the non idealities due to the process variations.


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