An off-line reconfiguration method is proposed for pipelined ADCs to improve their fabrication yield. Some nonlinearities generated by op amps in pipelined ADC stages depend on their bandwidth, while their equivalent input-referred errors depend on the stage position. From these premises, the method is conceived as a two steps process. During the first step, an alternate-test based technique determines the best stage, from the bandwidth point of view, as the front-end stage. In the second step, analog residue path interconnections and a stage scaling are configured according to the results from the first step. This method has been verified for a 10-bits ADC, designed in a 65 nm CMOS technology, by means of Monte Carlo simulations, with promising results.
A 1.0-V 10-b 30-MS/s 3.4-mW rail-to-rail pipelined ADC using a new front-end MDAC
