Cache Design for Low Power and High Yield

9th International Symposium on Quality Electronic Design (isqed 2008) ◽

10.1109/isqed.2008.4479707 ◽

2008 ◽

Author(s):

Baker Mohammad ◽

Martin Saint-Laurent ◽

Paul Bassett ◽

Jacob Abraham

Keyword(s):

Low Power ◽

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Low-Power Cache Design

Low-Power Electronics Design ◽

10.1201/9781420039559-32 ◽

2018 ◽

pp. 455-476

Keyword(s):

Low Power ◽

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A Low-Power Instruction Cache Design Based on Record Buffer

Journal of Computer Research and Development ◽

10.1360/crad20060426 ◽

2006 ◽

Vol 43 (4) ◽

pp. 744

Author(s):

Zhiqiang Ma

Keyword(s):

Low Power ◽

Instruction Cache ◽

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Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing

2013 IEEE 10th International Conference on ASIC ◽

10.1109/asicon.2013.6811968 ◽

2013 ◽

Author(s):

Ningxi Liu ◽

Yu Jiang ◽

Qing Dong ◽

Hui Li ◽

Xinyi Hu ◽

...

Keyword(s):

Low Power ◽

Adaptive Boosting ◽

Capacitance Variation ◽

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Low power instruction cache design based on branch execution tracks

2013 IEEE 10th International Conference on ASIC ◽

10.1109/asicon.2013.6811822 ◽

2013 ◽

Author(s):

Quanquan Li ◽

Qi Wang ◽

Tiejun Zhang ◽

Donghui Wang ◽

Chaohuan Hou

Keyword(s):

Low Power ◽

Instruction Cache ◽

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A low-power i-cache design with tag-comparison reuse

2004 International Symposium on System-on-Chip, 2004. Proceedings. ◽

10.1109/issoc.2004.1411147 ◽

2005 ◽

Author(s):

K. Inoue ◽

H. Tanaka ◽

V.G. Moshnyaga ◽

K. Murakami

Keyword(s):

Low Power ◽

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Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices

2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation ◽

10.1109/icsamos.2008.4664855 ◽

2008 ◽

Author(s):

Mohammad A Makhzan ◽

Ahmed Eltawil ◽

Fadi J. Kurdahi

Keyword(s):

Low Power ◽

Fault Tolerant ◽

Algorithm Level

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Low-Power Cache Design

Low-Power Processors and Systems on Chips ◽

10.1201/9781315220581-8 ◽

2018 ◽

pp. 8-1-8-21

Author(s):

Vasily G. Moshnyaga ◽

Koji Inoue

Keyword(s):

Low Power ◽

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Low-Power Cache Design Using 7T SRAM Cell

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ◽

10.1109/tcsii.2006.877276 ◽

2007 ◽

Vol 54 (4) ◽

pp. 318-322 ◽

Author(s):

Ramy E. Aly ◽

Magdy A. Bayoumi

Keyword(s):

Low Power ◽

Sram Cell ◽

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A new 6-transistor SRAM cell for low power cache design

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology ◽

10.1109/icsict.2012.6467902 ◽

2012 ◽

Author(s):

Yuan-Yuan Wang ◽

Zi-Ou Wang ◽

Li-Jun Zhang

Keyword(s):

Low Power ◽

Sram Cell ◽

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Low- Power Cache Design

Computer Engineering Series - Low-Power Electronics Design ◽

10.1201/9781420039559.ch25 ◽

2004 ◽

pp. 25-1-25-21

Author(s):

Vasily Moshnyaga ◽

Koji Inoue

Keyword(s):

Low Power ◽

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