Formal Verification Aware Redundant Sequential Logic Optimization to Improve Design Utilization

2021 22nd International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed51717.2021.9424336 ◽

2021 ◽

Author(s):

Rushabh Shah ◽

Krishna Agrawal

Keyword(s):

Formal Verification ◽

Improve Design ◽

Logic Optimization ◽

Sequential Logic

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A Low-Latency SC Polar Decoder Based on The Sequential Logic Optimization

2018 15th International Symposium on Wireless Communication Systems (ISWCS) ◽

10.1109/iswcs.2018.8491226 ◽

2018 ◽

Author(s):

Xin Bian ◽

Jincheng Dai ◽

Kai Niu ◽

Zhiqiang He

Keyword(s):

Low Latency ◽

Logic Optimization ◽

Sequential Logic

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On the optimization power of redundancy addition and removal for sequential logic optimization

Proceedings Euromicro Symposium on Digital Systems Design ◽

10.1109/dsd.2001.952305 ◽

2002 ◽

Author(s):

E.S. Millan ◽

L. Entrena ◽

J.A. Espejo

Keyword(s):

Logic Optimization ◽

Sequential Logic

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An ATPG-based approach to sequential logic optimization

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers ◽

10.1109/iccad.1991.185279 ◽

2002 ◽

Author(s):

K.-T. Cheng

Keyword(s):

Logic Optimization ◽

Sequential Logic

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Integrating symbolic techniques in ATPG-based sequential logic optimization

Proceedings of the conference on Design, automation and test in Europe - DATE '99 ◽

10.1145/307418.307555 ◽

1999 ◽

Author(s):

Enrique San Millán ◽

Luis Entrena ◽

José A. Espejo ◽

Silvia Chiusano ◽

Fulvio Corno

Keyword(s):

Logic Optimization ◽

Sequential Logic

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Precomputation-based sequential logic optimization for low power

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.335011 ◽

1994 ◽

Vol 2 (4) ◽

pp. 426-436 ◽

Author(s):

M. Alidina ◽

J. Monteiro ◽

S. Devadas ◽

A. Ghosh ◽

M. Papaefthymiou

Keyword(s):

Low Power ◽

Logic Optimization ◽

Sequential Logic

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Integrating symbolic techniques in ATPG-based sequential logic optimization

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761175 ◽

2003 ◽

Author(s):

E. San Millan ◽

L. Entrena ◽

J.A. Espejo ◽

S. Chiusano ◽

F. Corno

Keyword(s):

Logic Optimization ◽

Sequential Logic

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Retiming-based factorization for sequential logic optimization

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/348019.348068 ◽

2000 ◽

Vol 5 (3) ◽

pp. 373-398 ◽

Author(s):

Surendra Bommu ◽

Niall O'Neill ◽

Maciej Ciesielski

Keyword(s):

Logic Optimization ◽

Sequential Logic

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Combinational and sequential logic optimization by redundancy addition and removal

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.391740 ◽

1995 ◽

Vol 14 (7) ◽

pp. 909-916 ◽

Author(s):

L.A. Entrena ◽

Kwang-Ting Cheng

Keyword(s):

Logic Optimization ◽

Sequential Logic

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Sequential logic optimization by redundancy addition and removal

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1993.580074 ◽

2002 ◽

Author(s):

L. Entrena ◽

K.-T. Cheng

Keyword(s):

Logic Optimization ◽

Sequential Logic

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Precomputation-based Sequential Logic Optimization For Low Power

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629747 ◽

2005 ◽

Author(s):

M. Alidina ◽

J. Monteiro ◽

S. Devadas ◽

A. Ghosh ◽

M. Papefthymiou

Keyword(s):

Low Power ◽

Logic Optimization ◽

Sequential Logic

Download Full-text