Precomputation-based sequential logic optimization for low power

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.335011 ◽

1994 ◽

Vol 2 (4) ◽

pp. 426-436 ◽

Author(s):

M. Alidina ◽

J. Monteiro ◽

S. Devadas ◽

A. Ghosh ◽

M. Papaefthymiou

Keyword(s):

Low Power ◽

Logic Optimization ◽

Sequential Logic

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Precomputation-based Sequential Logic Optimization For Low Power

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629747 ◽

2005 ◽

Author(s):

M. Alidina ◽

J. Monteiro ◽

S. Devadas ◽

A. Ghosh ◽

M. Papefthymiou

Keyword(s):

Low Power ◽

Logic Optimization ◽

Sequential Logic

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Sequential logic optimization for low power using input-disabling precomputation architectures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.700725 ◽

1998 ◽

Vol 17 (3) ◽

pp. 279-284 ◽

Author(s):

J. Monteiro ◽

S. Devadas ◽

A. Ghosh

Keyword(s):

Low Power ◽

Logic Optimization ◽

Sequential Logic

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A Low-Latency SC Polar Decoder Based on The Sequential Logic Optimization

2018 15th International Symposium on Wireless Communication Systems (ISWCS) ◽

10.1109/iswcs.2018.8491226 ◽

2018 ◽

Author(s):

Xin Bian ◽

Jincheng Dai ◽

Kai Niu ◽

Zhiqiang He

Keyword(s):

Low Latency ◽

Logic Optimization ◽

Sequential Logic

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Design and analysis of adiabatic complex sequential logic circuits in sub-threshold regime for ultra-low power application

2016 International Conference on Communication and Signal Processing (ICCSP) ◽

10.1109/iccsp.2016.7754506 ◽

2016 ◽

Author(s):

Manash Chanda ◽

Diptansu Sinha ◽

Jeet Basak ◽

Tanushree Ganguli ◽

Chandan K. Sarkar

Keyword(s):

Low Power ◽

Logic Circuits ◽

Ultra Low Power ◽

Sequential Logic ◽

Power Application ◽

Threshold Regime

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On the optimization power of redundancy addition and removal for sequential logic optimization

Proceedings Euromicro Symposium on Digital Systems Design ◽

10.1109/dsd.2001.952305 ◽

2002 ◽

Author(s):

E.S. Millan ◽

L. Entrena ◽

J.A. Espejo

Keyword(s):

Logic Optimization ◽

Sequential Logic

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A low-power logic optimization methodology based on a fast power-driven mapping

Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273) ◽

10.1109/iccd.1998.727039 ◽

2002 ◽

Author(s):

S. Roy ◽

H. Arts ◽

P. Banerjee

Keyword(s):

Low Power ◽

Logic Optimization ◽

Optimization Methodology ◽

Low Power Logic

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NEM Relay-Based Sequential Logic Circuits for Low-Power Design

IEEE Transactions on Nanotechnology ◽

10.1109/tnano.2013.2252923 ◽

2013 ◽

Vol 12 (3) ◽

pp. 386-398 ◽

Author(s):

Ramakrishnan Venkatasubramanian ◽

Sujan K. Manohar ◽

Poras T. Balsara

Keyword(s):

Low Power ◽

Low Power Design ◽

Logic Circuits ◽

Sequential Logic

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Circuit activity driven multilevel logic optimization for low power reliable operation

1993 European Conference on Design Automation with the European Event in ASIC Design ◽

10.1109/edac.1993.386448 ◽

2002 ◽

Author(s):

S.C. Prasad ◽

K. Roy

Keyword(s):

Low Power ◽

Reliable Operation ◽

Logic Optimization

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Influence of BA4047 filler addition through Mamdani fuzzy logic optimization for double-sided T-joint welding of aluminum alloys using low-power fiber laser

The International Journal of Advanced Manufacturing Technology ◽

10.1007/s00170-017-0695-1 ◽

2017 ◽

Vol 93 (5-8) ◽

pp. 2133-2143 ◽

Author(s):

Shamini Janasekaran ◽

Mohd Fadzil Jamaludin ◽

Farazila Yusof ◽

Mohd Hamdi Abdul Shukor ◽

Tadashi Ariga

Keyword(s):

Fuzzy Logic ◽

Aluminum Alloys ◽

Low Power ◽

Fiber Laser ◽

Logic Optimization

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Correction to "An Approach for Multilevel Logic Optimization Targeting Low Power"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.1996.536724 ◽

1996 ◽

Vol 15 (9) ◽

pp. 1176

Author(s):

M. Pedram ◽

S. Iman

Keyword(s):

Low Power ◽

Logic Optimization

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