Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)
Latest Publications

TOTAL DOCUMENTS

140

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE Comput. Soc

0769500781

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

An Efficient And Flexible Methodology For Modelling And Simulation Of Heterogeneous Mechatronic Systems

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761227 ◽

2005 ◽

Author(s):

S. Scherber ◽

C. Mfiller-Schloer

Keyword(s):

Modelling And Simulation ◽

Mechatronic Systems

ATPG tools for Delay Faults at the Functional Level *

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761195 ◽

2005 ◽

Author(s):

S. Tragoudas ◽

M. Michael

Keyword(s):

Delay Faults ◽

Functional Level

Virtual Socket Interface Alliance

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761118 ◽

2005 ◽

Cited By ~ 1

Author(s):

R. Seepold

Keyword(s):

Socket Interface

Single Chip Or Hybrid System Integration

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761192 ◽

2005 ◽

Author(s):

I. Bolsens

Keyword(s):

Hybrid System ◽

System Integration ◽

Single Chip

An analog performance estimator for improving the effectiveness of CMOS analog systems circuit synthesis

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761156 ◽

2003 ◽

Cited By ~ 2

Author(s):

A. Nunez-Aldana ◽

R. Vemuri

Keyword(s):

Circuit Synthesis ◽

Analog Performance ◽

Analog Systems

Illegal state space identification for sequential circuit test generation

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761213 ◽

2003 ◽

Cited By ~ 8

Author(s):

M. Konijnenburg ◽

J. van der Linden ◽

A. van de Goor

Keyword(s):

State Space ◽

Test Generation ◽

Sequential Circuit

Variable reordering for shared binary decision diagrams using output probabilities

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761217 ◽

2003 ◽

Author(s):

M.A. Thornton ◽

J.P. Williams ◽

R. Drechsler ◽

N. Drechsler

Keyword(s):

Binary Decision Diagrams ◽

Decision Diagrams ◽

Binary Decision

A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761145 ◽

2003 ◽

Cited By ~ 3

Author(s):

H. Sasaki

Keyword(s):

Formal Semantics ◽

State Machine ◽

Abstract State Machine

Codex-dp: co-design of communicating systems using dynamic programming

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761184 ◽

2003 ◽

Cited By ~ 1

Author(s):

Jui-Ming Chang ◽

M. Pedram

Keyword(s):

Dynamic Programming

Efficient switching activity simulation under a real delay model using a bitparallel approach

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761166 ◽

2003 ◽

Cited By ~ 1

Author(s):

M. Buhler ◽

M. Papesch ◽

K. Kapp ◽

U.G. Baitinger

Keyword(s):

Delay Model ◽

Switching Activity

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

An Efficient And Flexible Methodology For Modelling And Simulation Of Heterogeneous Mechatronic Systems

ATPG tools for Delay Faults at the Functional Level *

Virtual Socket Interface Alliance

Single Chip Or Hybrid System Integration

An analog performance estimator for improving the effectiveness of CMOS analog systems circuit synthesis

Illegal state space identification for sequential circuit test generation

Variable reordering for shared binary decision diagrams using output probabilities

A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine

Codex-dp: co-design of communicating systems using dynamic programming

Efficient switching activity simulation under a real delay model using a bitparallel approach

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)
Latest Publications