High performance MEMS accelerometer and gyro with a unique SMD and digital interface

2021 ◽  
Author(s):  
A. Filipe ◽  
V. Gaff ◽  
W. Unrau ◽  
W. Schreiber-Prillwitz ◽  
Y. David
Keyword(s):  
High Performance ◽  
Digital Interface ◽  
Mems Accelerometer

scholarly journals A High-Performance Digital Interface Circuit for a High-Q Micro-Electromechanical System Accelerometer

Micromachines ◽  
2018 ◽  
Vol 9 (12) ◽  
pp. 675 ◽  
Author(s):  
Xiangyu Li ◽  
Jianping Hu ◽  
Xiaowei Liu
Keyword(s):  
High Performance ◽  
Low Noise ◽  
Electromechanical System ◽  
Digital Interface ◽  
Interface Circuit ◽  
Mems Accelerometer ◽  
High Q ◽  
Front End ◽  
Micro Electromechanical System ◽  
Micro Accelerometer

Micro-electromechanical system (MEMS) accelerometers are widely used in the inertial navigation and nanosatellites field. A high-performance digital interface circuit for a high-Q MEMS micro-accelerometer is presented in this work. The mechanical noise of the MEMS accelerometer is decreased by the application of a vacuum-packaged sensitive element. The quantization noise in the baseband of the interface circuit is greatly suppressed by a 4th-order loop shaping. The digital output is attained by the interface circuit based on a low-noise front-end charge-amplifier and a 4th-order Sigma-Delta (ΣΔ) modulator. The stability of high-order ΣΔ was studied by the root locus method. The gain of the integrators was reduced by using the proportional scaling technique. The low-noise front-end detection circuit was proposed with the correlated double sampling (CDS) technique to eliminate the 1/f noise and offset. The digital interface circuit was implemented by 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology. The high-performance digital accelerometer system was implemented by double chip integration and the active interface circuit area was about 3.3 mm × 3.5 mm. The high-Q MEMS accelerometer system consumed 10 mW from a single 5 V supply at a sampling frequency of 250 kHz. The micro-accelerometer system could achieve a third harmonic distortion of −98 dB and an average noise floor in low-frequency range of less than −140 dBV; a resolution of 0.48 μg/Hz1/2 (@300 Hz); a bias stability of 18 μg by the Allen variance program in MATLAB.

scholarly journals Giga-bit VLBI Data Recorder, New Concept of Formatter Independent

1998 ◽  
Vol 164 ◽  
pp. 395-396
Author(s):  
J. Nakajima ◽  
Y. Koyama ◽  
M. Sekido ◽  
H. Kiuchi ◽  
S. Hama ◽  
...  
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Digital Technology ◽  
High Speed ◽  
High Performance ◽  
Scientific Field ◽  
Recording System ◽  
Digital Interface ◽  
Vlbi Data ◽  
Bit Stream

AbstractA high performance VLBI recorder project using advanced digital technology started in 1995. TOSHIBA GBR 1000 and VLBI interface define 32 parallel, 32 MHz clock standard digital interface and support transparent recording/play-back to extremely high-speed digital bit stream. This is the formatter independent scientific recording bind the UTC to observed data. This highly reliable, low-bit-error-rate (10−16) recording system is also expected to be used in other scientific field. For the first example to examine the recorder performance in VLBI, we had been prepared 1024 Mbps sampler (256/512/1024 MSps, 2 bit, 4/2/1 ch). And here, an experimental giga-bit correlator specification for these VLBI acquisition system is introduced.

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