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0.5 mu m BiCMOS standard-cell macros including 0.5 W 3 ns register file and 0.6 W 5 ns 32 kB cache
1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers
◽
10.1109/isscc.1992.200403
◽
2003
◽
Author(s):
H. Kara
◽
T. Sakurai
◽
T. Nagamatsu
◽
S. Kobayashi
◽
K. Seta
◽
...
Keyword(s):
Standard Cell
◽
Register File
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24.4 A 5nm
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4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue
2021 IEEE International Solid- State Circuits Conference (ISSCC)
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10.1109/isscc42613.2021.9366000
◽
2021
◽
Author(s):
Hidehiro Fujiwara
◽
Yi-Hsin Nien
◽
Chih-Yu Lin
◽
Hsien-Yu Pan
◽
Hao-Wen Hsu
◽
...
Keyword(s):
Standard Cell
◽
Register File
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Instruction Scheduling Algorithm for Register File Connectivity Clustered VLIW Architecture
Chinese Journal of Computers
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10.3724/sp.j.1016.2008.00127
◽
2009
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Vol 31
(1)
◽
pp. 127-132
Author(s):
Zhi-Xiong ZHOU
◽
Hu HE
◽
Xu YANG
◽
Yan-Jun ZHANG
◽
Yi-He SUN
Keyword(s):
Scheduling Algorithm
◽
Instruction Scheduling
◽
Register File
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Active-Cycle Based Register File Design for Reduced Ports and Energy
Chinese Journal of Computers
◽
10.3724/sp.j.1016.2008.00299
◽
2009
◽
Vol 31
(2)
◽
pp. 299-308
◽
Cited By ~ 1
Author(s):
Yu-Lai ZHAO
◽
Xian-Feng LI
◽
Dong TONG
◽
Han-Xin SUN
◽
Jie CHEN
◽
...
Keyword(s):
Register File
◽
File Design
Download Full-text
Standard-Cell, Open-Architecture Power Conversion Systems
10.21236/ada468619
◽
2005
◽
Author(s):
D. Boroyevich
◽
F. Wang
◽
F. C. Lee
◽
W. G. Odendaal
◽
S. Edwards
Keyword(s):
Power Conversion
◽
Open Architecture
◽
Standard Cell
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Register/ file/ cache microarchitecture study using VHDL
Proceedings of the 24th annual international symposium on Microarchitecture - MICRO 24
◽
10.1145/123465.123510
◽
1991
◽
Author(s):
Samarina Makhdoom
◽
Daniel Tabak
◽
Richard Auletta
Keyword(s):
Register File
◽
File Cache
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Power and Variation Improved Near-Vt Standard Cell Library for 28-nm FDSOI
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
◽
10.1109/s3s46989.2019.9320687
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2019
◽
Author(s):
Wing-Tsi Wong
◽
Kamlesh Singh
◽
Jos Huisken
◽
Jose Pineda de Gyvez
Keyword(s):
Standard Cell
◽
Standard Cell Library
◽
Cell Library
◽
28 Nm
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A 15000 Tuning Range Scalable Feed-Forward Oscillator With 0.05mm2 Area in CMOS Standard-Cell Format
2021 IEEE International Symposium on Circuits and Systems (ISCAS)
◽
10.1109/iscas51556.2021.9401776
◽
2021
◽
Author(s):
Julian Arenas
◽
Juan Sebastian Moya
◽
Elkim Roa
Keyword(s):
Tuning Range
◽
Standard Cell
◽
Feed Forward
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Superconductor Standard Cell Library for Advanced EDA Design Flow
IEEE Transactions on Applied Superconductivity
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10.1109/tasc.2021.3061024
◽
2021
◽
pp. 1-1
Author(s):
Sukanya Sagarika Meher
◽
Jushya Ravi
◽
Mustafa Eren Celik
◽
Stephen Miller
◽
Anubhav Sahu
◽
...
Keyword(s):
Design Flow
◽
Standard Cell
◽
Standard Cell Library
◽
Cell Library
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NMLib: A Nanomagnetic Logic Standard Cell Library
2021 IEEE International Symposium on Circuits and Systems (ISCAS)
◽
10.1109/iscas51556.2021.9401107
◽
2021
◽
Author(s):
Laysson Oliveira Luz
◽
Jose Augusto M. Nacif
◽
Ricardo S. Ferreira
◽
Omar P. Vilela Neto
Keyword(s):
Standard Cell
◽
Standard Cell Library
◽
Nanomagnetic Logic
◽
Cell Library
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Cross-Corner Delay Variation Model for Standard Cell Libraries
IEEE Access
◽
10.1109/access.2021.3080294
◽
2021
◽
pp. 1-1
Author(s):
Kwangsu Kim
◽
Byungha Joo
◽
Young Min Park
◽
Taeyang Jeong
◽
Ki Tae Kim
◽
...
Keyword(s):
Standard Cell
◽
Delay Variation
◽
Variation Model
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