A parallel VLSI algorithm for a high throughput systolic array VLSI implementation of type IV DCT

2009 ◽  
Author(s):  
Doru Florin Chiper
Keyword(s):  
High Throughput ◽  
Systolic Array ◽  
Vlsi Implementation ◽  
Type Iv ◽  
Vlsi Algorithm

scholarly journals A new VLSI algorithm and architecture for the hardware implementation of type IV discrete cosine transform using a pseudo-band correlation structure

2011 ◽  
Vol 1 (2) ◽  
Author(s):  
Doru Chiper
Keyword(s):  
Discrete Cosine Transform ◽  
Systolic Array ◽  
Correlation Structure ◽  
Efficient Design ◽  
Hardware Complexity ◽  
Cosine Transform ◽  
Type Iv ◽  
Vlsi Chip ◽  
Array Architecture ◽  
Vlsi Algorithm

AbstractA new VLSI algorithm and its associated systolic array architecture for a prime length type IV discrete cosine transform is presented. They represent the basis of an efficient design approach for deriving a linear systolic array architecture for type IV DCT. The proposed algorithm uses a regular computational structure called pseudoband correlation structure that is appropriate for a VLSI implementation. The proposed algorithm is then mapped onto a linear systolic array with a small number of I/O channels and low I/O bandwidth. The proposed architecture can be unified with that obtained for type IV DST due to a similar kernel. A highly efficient VLSI chip can be thus obtained with good performance in the architectural topology, computing parallelism, processing speed, hardware complexity and I/O costs similar to those obtained for circular correlation and cyclic convolution computational structures.

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