Two-level pipelined systolic array can attain parallelism down to lower levels and provide much higher throughput and computational speed than conventional ones. This paper presents a design procedure starting from an algorithm representation, called Dependence Graph (DG). Arrays with different performances can be obtained by applying the various linear transformation matrices on DG. Image resampling is a process for image construction and display. It has important applications in image processing or in digital TV. In this paper, two design considerations are applied to build high-performance VLSI image resampler. First, two-level pipelined systolic array is designed to maximize parallelism and also make VLSI implementation highly feasible. Second, a modified two-pass resampling scheme is devised to reduce the amount of required storage and increase the concurrency between two passes of resampling. This image resampler can get a throughput of one pixel per clock period being smaller than the latency of an adder. The requirement for storage is only several line buffers.
A new VLSI algorithm and architecture for the hardware implementation of type IV discrete cosine transform using a pseudo-band correlation structure