A hardware implementation for real-time lane detection using high-level synthesis

Author(s):  
Chanon Khongprasongsiri ◽  
Pinit Kumhom ◽  
Watcharapan Suwansantisuk ◽  
Teerasak Chotikawanid ◽  
Surachate Chumpol ◽  
...  
2021 ◽  
Vol 9 (1) ◽  
pp. 280-287
Author(s):  
Minal Deshmukh, Prasad Khandekar, Nishikant Sadafale

Image Processing is a significantly desirable in commercial, industrial, and medical applications. Processor based architectures are inappropriate for real time applications as Image processing algorithms are quite intensive in terms of computations. To reduce latency and limitation in performance due to limited amount of memory and fixed clock frequency for synthesis in processor-based architecture, FPGA can be used in smart devices for implementing real time image processing applications. To increase speed of real time image processing custom overlays (Hardware Library of programmable logic circuit) can be designed to run on FPGA fabric. The IP core generated by the HLS (High Level Synthesis) can be implemented on a reconfigurable platform which allows effective utilization of channel bandwidth and storage. In this paper we have presented FPGA overlay design for color transformation function using Xilinx’s python productivity board PYNQ-Z2 to get benefit in performance over a traditional processor. Performance comparison of custom overlay on FPGA and Processor based platform shows FPGA execution yields minimum computation time.


2019 ◽  
Vol 2019 (16) ◽  
pp. 1217-1220 ◽  
Author(s):  
Qiao Li ◽  
Yinxing Xiang ◽  
Qing Mu ◽  
Xing Zhang ◽  
Xiongfei Li ◽  
...  

2017 ◽  
Vol 50 ◽  
pp. 26-38 ◽  
Author(s):  
Affaq Qamar ◽  
Fahad Bin Muslim ◽  
Javed Iqbal ◽  
Luciano Lavagno

2018 ◽  
pp. 1133-1154
Author(s):  
Ahmed Abouelfarag ◽  
Marwa Ali Elshenawy ◽  
Esraa Alaaeldin Khattab

Recently, computer vision is playing an important role in many essential human-computer interactive applications, these applications are subject to a “real-time” constraint, and therefore it requires a fast and reliable computational system. Edge Detection is the most used approach for segmenting images based on changes in intensity. There are various kernels used to perform edge detection, such as: Sobel, Robert, and Prewitt, upon which, the most commonly used is Sobel. In this research a novel type of operator cells that perform addition is introduced to achieve computational acceleration. The novel operator cells have been employed in the chosen FPGA Zedboard which is well-suited for real-time image and video processing. Accelerating the Sobel edge detection technique is exploited using different tools such as the High-Level Synthesis tools provided by Vivado. This enhancement shows a significant improvement as it decreases the computational time by 26% compared to the conventional adder cells.


Author(s):  
Ahmed Abouelfarag ◽  
Marwa Ali Elshenawy ◽  
Esraa Alaaeldin Khattab

Recently, computer vision is playing an important role in many essential human-computer interactive applications, these applications are subject to a “real-time” constraint, and therefore it requires a fast and reliable computational system. Edge Detection is the most used approach for segmenting images based on changes in intensity. There are various kernels used to perform edge detection, such as: Sobel, Robert, and Prewitt, upon which, the most commonly used is Sobel. In this research a novel type of operator cells that perform addition is introduced to achieve computational acceleration. The novel operator cells have been employed in the chosen FPGA Zedboard which is well-suited for real-time image and video processing. Accelerating the Sobel edge detection technique is exploited using different tools such as the High-Level Synthesis tools provided by Vivado. This enhancement shows a significant improvement as it decreases the computational time by 26% compared to the conventional adder cells.


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