Integrated Microwave Photonic Spectral Shaping for Linearization and Spurious-Free Dynamic Range Enhancement

AbstractA scheme to suppress nonlinear intermodulation distortion in microwave photonic (MWP) link is proposed by using polarizers to compensate inherent non-linear behavior of dual-electrode Mach-Zehnder modulator (DE-MZM). Insertion losses and extinction ratio have also been considered. Simulation results depict that spurious free dynamic range (SFDR) of proposed link reaches to 130.743 dB.Hz2/3. A suppression of 41 dB in third order intermodulation distortions and an improvement of 15.3 dB is reported when compared with the conventional link. In addition, an electrical spectrum at different polarization angles is extracted and 79^\circ is found to be optimum value of polarization angle.

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Frequency Multiplier-by-4 (Quadrupler) with 52 dB Spurious-Free Dynamic Range for 152 GHz to 220 GHz (G-Band) in 130 nm SiGe

2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) ◽

10.1109/rfic49505.2020.9218386 ◽

2020 ◽

Cited By ~ 1

Author(s):

Paul Starke ◽

Vincent Ries ◽

Corrado Carta ◽

Frank Ellinger

Keyword(s):

Dynamic Range ◽

Frequency Multiplier ◽

Spurious Free Dynamic Range ◽

Free Dynamic

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Low-power 1.25-GHZ signal bandwidth 4-bit CMOS analog-to-digital converter for high spurious-free dynamic range wideband communications

2007 IEEE International SOC Conference ◽

10.1109/socc.2007.4545438 ◽

2007 ◽

Author(s):

Mingzhen Wang ◽

Chien-In Henry Chen

Keyword(s):

Low Power ◽

Dynamic Range ◽

Analog To Digital Converter ◽

Digital Converter ◽

Analog To Digital ◽

Spurious Free Dynamic Range ◽

Wideband Communications ◽

Free Dynamic

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Large Spurious-free Dynamic Range RoF Link with Tunable CSR

10.1109/vtc2021-fall52928.2021.9625574 ◽

2021 ◽

Author(s):

Ruiqiong Wang ◽

Yangyu Fan ◽

Jiajun Tan ◽

Yongsheng Gao

Keyword(s):

Dynamic Range ◽

Spurious Free Dynamic Range ◽

Free Dynamic

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Synergy Micro-Electronics Technology with a High Linearity BiCMOS Sample-and-Hold Circuit

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.473.50 ◽

2013 ◽

Vol 473 ◽

pp. 50-53

Author(s):

Jie Lin ◽

Fei Yan Mu

Keyword(s):

Dynamic Range ◽

Harmonic Distortion ◽

High Accuracy ◽

Pipeline Adc ◽

Nonlinearity Error ◽

Front End ◽

Sample And Hold ◽

Spurious Free Dynamic Range ◽

Bicmos Process ◽

Free Dynamic

A high accuracy BiCMOS sample and hold (S/H) circuit employed in the front end of a12bit 10 MS/s Pipeline ADC is presented. To reduce the nonlinearity error cause by the sampling switch, a signal dependent clock bootstrapping system is introduced. It is implemented using 0.6 um BiCMOS process. An 88.77 dB spurious-free dynamic range (SFDR), and a -105.20 dB total harmonic distortion (THD) are obtained.

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