Low-power 1.25-GHZ signal bandwidth 4-bit CMOS analog-to-digital converter for high spurious-free dynamic range wideband communications

A 13-bit analog-to-digital converter (ADC) is designed in 0.35 μm CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 μm technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm–0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply.

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Effects of ADC Nonlinearity on the Spurious Dynamic Range Performance of Compressed Sensing

The Scientific World JOURNAL ◽

10.1155/2014/143693 ◽

2014 ◽

Vol 2014 ◽

pp. 1-6 ◽

Cited By ~ 1

Author(s):

Rongzong Kang ◽

Pengwu Tian ◽

Hongyi Yu

Keyword(s):

Compressed Sensing ◽

Dynamic Range ◽

Dynamic Performance ◽

Digital Converter ◽

Analog To Digital ◽

Sensing System ◽

Spurious Free Dynamic Range ◽

Simulation Results ◽

The Impact ◽

Free Dynamic

Analog-to-information converter (AIC) plays an important role in the compressed sensing system; it has the potential to significantly extend the capabilities of conventional analog-to-digital converter. This paper evaluates the impact of AIC nonlinearity on the dynamic performance in practical compressed sensing system, which included the nonlinearity introduced by quantization as well as the circuit non-ideality. It presents intuitive yet quantitative insights into the harmonics of quantization output of AIC, and the effect of other AIC nonlinearity on the spurious dynamic range (SFDR) performance is also analyzed. The analysis and simulation results demonstrated that, compared with conventional ADC-based system, the measurement process decorrelates the input signal and the quantization error and alleviate the effect of other decorrelates of AIC, which results in a dramatic increase in spurious free dynamic range (SFDR).

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Design of Low Voltage Low Power ADC for WSN Node

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.760-762.561 ◽

2013 ◽

Vol 760-762 ◽

pp. 561-566

Author(s):

Si Kui Ren ◽

Zhi Qun Li

Keyword(s):

Low Power ◽

Figure Of Merit ◽

Dynamic Range ◽

Low Voltage ◽

Cmos Technology ◽

Total Power ◽

Chip Area ◽

Analog To Digital ◽

Spurious Free Dynamic Range ◽

Free Dynamic

This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

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AN OPTIMIZED LOW POWER PIPELINE ANALOG-TO-DIGITAL CONVERTER FOR HIGH-SPEED WLAN APPLICATION

Journal of Circuits System and Computers ◽

10.1142/s0218126614500595 ◽

2014 ◽

Vol 23 (05) ◽

pp. 1450059 ◽

Cited By ~ 2

Author(s):

MAO YE ◽

BIN WU ◽

YONGXU ZHU ◽

YUMEI ZHOU

Keyword(s):

Low Power ◽

Power Dissipation ◽

High Speed ◽

Dynamic Range ◽

Cmos Process ◽

Area Network ◽

Analog To Digital Converter ◽

Digital Converter ◽

Silicon Area ◽

Analog To Digital

This paper presents the design and implementation of a 11-bit 160 MSPS analog-to-digital converter (ADC) for next generation super high-speed wireless local area network (WLAN) application. The ADC core consists of one front sample and hold stage and four cascades of 2.5 bit pipeline stages with opamp sharing between successive stages. To achieve low power dissipation at 1.2 V supply, a single stage symmetrical amplifier with double transimpedance gain-boosting amplifier is proposed. High speed on-chip reference buffer with replica source follower is also included for linearity performance. The ADC was fabricated in a standard 130-nm CMOS process and an occupied silicon area of 0.95 mm × 1.15 mm. Performance of 73 dB spurious-free-dynamic-range is measured at 160 MS/s with 1 Vpp input signal. The power dissipation of the analog core chip is only 50 mW from a 1.2 V supply.

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