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Analysis of NAND/NOR gates using subthreshold adiabatic logic (SAL) for ultra low power applications
2016 International Conference on Microelectronics, Computing and Communications (MicroCom)
◽
10.1109/microcom.2016.7522472
◽
2016
◽
Cited By ~ 2
Author(s):
Manash Chanda
◽
Rounak Dutta
◽
Aliyasmin Rahaman
◽
Chandan Kumar Sarkar
Keyword(s):
Low Power
◽
Ultra Low Power
◽
Adiabatic Logic
Download Full-text
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References
Modified positive feedback adiabatic logic for ultra low power VLSI
2015 International Conference on Computer, Communication and Control (IC4)
◽
10.1109/ic4.2015.7375579
◽
2015
◽
Cited By ~ 6
Author(s):
Shiv Pratap Singh Kushawaha
◽
Trailokya Nath Sasamal
Keyword(s):
Low Power
◽
Positive Feedback
◽
Ultra Low Power
◽
Adiabatic Logic
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An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications
Analog Integrated Circuits and Signal Processing
◽
10.1007/s10470-019-01561-4
◽
2019
◽
Vol 102
(1)
◽
pp. 111-123
◽
Cited By ~ 4
Author(s):
Sanjay Vidhyadharan
◽
Ramakant Yadav
◽
Simhadri Hariprasad
◽
Surya Shankar Dan
Keyword(s):
Low Power
◽
Ultra Low Power
◽
Sensor Applications
◽
Tunnel Fet
◽
Adiabatic Logic
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A Novel Technique in Adiabatic Logic for Ultra Low Power IN DSM Technology
2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE)
◽
10.1109/icrieece44171.2018.9008430
◽
2018
◽
Author(s):
Mohd. Farid Khan
◽
Uday Panwar
Keyword(s):
Low Power
◽
Ultra Low Power
◽
Novel Technique
◽
Adiabatic Logic
Download Full-text
Modified ECRL Adiabatic Logic for Ultra Low Power VLSI Applications
10.1109/iceeict53905.2021.9667847
◽
2021
◽
Author(s):
Mohammad Redwan Islam
◽
Takibul Islam Sabbi
◽
Nafiul Islam Ananta
◽
Saroar Jaman Badhon
◽
Satyendra N. Biswas
Keyword(s):
Low Power
◽
Ultra Low Power
◽
Adiabatic Logic
Download Full-text
Modified Positive Feedback Adiabatic Logic for Ultra Low Power Adder
2016 Second International Conference on Computational Intelligence & Communication Technology (CICT)
◽
10.1109/cict.2016.80
◽
2016
◽
Author(s):
Shiv Pratap Singh Kushawaha
◽
Trailokya Nath Sasamal
Keyword(s):
Low Power
◽
Positive Feedback
◽
Ultra Low Power
◽
Adiabatic Logic
Download Full-text
Ultra Low Power Adiabatic Logic Using Diode Connected DC Biased PFAL Logic
Advances in Electrical and Electronic Engineering
◽
10.15598/aeee.v15i1.1974
◽
2017
◽
Vol 15
(1)
◽
Cited By ~ 1
Author(s):
Akash Agrawal
◽
Tarun Kumar Gupta
◽
Ajay Kumar Dadoria
Keyword(s):
Low Power
◽
Ultra Low Power
◽
Adiabatic Logic
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A novel efficient adiabatic logic design for ultra low power
2016 International Conference on ICT in Business Industry & Government (ICTBIG)
◽
10.1109/ictbig.2016.7892723
◽
2016
◽
Author(s):
Akash Agrawal
◽
Tarun Kumar Gupta
◽
Ajay Kumar Dadoria
◽
Deepak Kumar
Keyword(s):
Low Power
◽
Logic Design
◽
Ultra Low Power
◽
Adiabatic Logic
Download Full-text
An Ultra Low Power VLSI Architecture for Viterbi Decoder using Subthreshold Adiabatic Logic
2018 International Conference on Intelligent Computing and Communication for Smart World (I2C2SW)
◽
10.1109/i2c2sw45816.2018.8997189
◽
2018
◽
Author(s):
M. Ruban Gladwin
◽
N. Kasthuri
Keyword(s):
Low Power
◽
Vlsi Architecture
◽
Viterbi Decoder
◽
Ultra Low Power
◽
Adiabatic Logic
Download Full-text
Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications
Microelectronics Journal
◽
10.1016/j.mejo.2019.104601
◽
2019
◽
Vol 92
◽
pp. 104601
◽
Cited By ~ 3
Author(s):
B.P. Bhuvana
◽
V.S. Kanchana Bhaaskaran
Keyword(s):
Low Power
◽
Energy Efficient
◽
Ultra Low Power
◽
Adiabatic Logic
◽
Pass Transistor
◽
Efficient Pass
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Design and analysis of adiabatic logic in sub-threshold regime for ultra low power application
2016 Conference on Emerging Devices and Smart Systems (ICEDSS)
◽
10.1109/icedss.2016.7587692
◽
2016
◽
Author(s):
Manash Chanda
◽
Diptansu Sinha
◽
Jeet Basak
◽
Tanushree Ganguli
◽
Chandan K. Sarkar
Keyword(s):
Low Power
◽
Ultra Low Power
◽
Adiabatic Logic
◽
Power Application
◽
Threshold Regime
Download Full-text
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