Modified Positive Feedback Adiabatic Logic for Ultra Low Power Adder

2016 ◽  
Author(s):  
Shiv Pratap Singh Kushawaha ◽  
Trailokya Nath Sasamal
Keyword(s):  
Low Power ◽  
Positive Feedback ◽  
Ultra Low Power ◽  
Adiabatic Logic

scholarly journals Energy Efficient Digital Circuit Based on Self Cascoding Positive Feedback Adiabatic Logic for Low Power VLSI Design

2019 ◽  
Vol 8 (2S11) ◽  
pp. 950-954
Keyword(s):  
Low Power ◽  
Positive Feedback ◽  
Vlsi Design ◽  
Digital Circuit ◽  
Operating Frequency ◽  
Threshold Region ◽  
Clock Frequency ◽  
Ultra Low Power ◽  
Prime Concern ◽  
Adiabatic Logic

Emphasis in VLSI design has shifted from high speed to low power due to the proliferation of portable electronic systems. The continuing decrease in feature size and corresponding increase in chip density and operating frequency have made power consumption as a prime concern in VLSI design. For ultra low power applications, the idea of self cascode positive feedback adiabatic logic (SC-PFAL) has reported as a promising candidate to reduce power dissipation at low operating frequency. To enhance the energy efficiency of the logic circuits, self cascoding of transistor is applied to charge recovery logic working in sub-threshold region. Based on this proposed technique, we design a basic MOS digital library cell. Simulation results are found using 70nm technology model file available from predictive technologies. At low clock frequency, the proposed logic i.e. SC-PFAL has significant improvement in terms of energy consumption than original PFAL.

An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications

2019 ◽  
Vol 102 (1) ◽  
pp. 111-123 ◽  
Author(s):  
Sanjay Vidhyadharan ◽  
Ramakant Yadav ◽  
Simhadri Hariprasad ◽  
Surya Shankar Dan
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
Sensor Applications ◽  
Tunnel Fet ◽  
Adiabatic Logic

Modified ECRL Adiabatic Logic for Ultra Low Power VLSI Applications

2021 ◽  
Author(s):  
Mohammad Redwan Islam ◽  
Takibul Islam Sabbi ◽  
Nafiul Islam Ananta ◽  
Saroar Jaman Badhon ◽  
Satyendra N. Biswas
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
Adiabatic Logic

Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design

Integration ◽  
2018 ◽  
Vol 62 ◽  
pp. 1-13 ◽  
Author(s):  
P. Singh ◽  
B.S. Reniwal ◽  
V. Vijayvargiya ◽  
V. Sharma ◽  
S.K. Vishvakarma
Keyword(s):  
Low Power ◽  
Positive Feedback ◽  
High Stability ◽  
Ultra Low Power ◽  
Look Up Table ◽  
Sram Cell
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