The circuit designs of an SRAM based look-up table for high performance FPGA architecture

2004 ◽  
Author(s):  
P. Mal ◽  
J.F. Cantin ◽  
F.R. Beyette
Keyword(s):  
High Performance ◽  
Look Up Table ◽  
Fpga Architecture

A high performance, high density sea of modules FPGA architecture

2002 ◽  
Author(s):  
K. El-Ayat ◽  
S. Kaptanoglu ◽  
R. Chan ◽  
J. Lien ◽  
W. Plants ◽  
...  
Keyword(s):  
High Performance ◽  
High Density ◽  
Fpga Architecture

A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers

2017 ◽  
Vol 5 (2) ◽  
pp. 210-222 ◽  
Author(s):  
Xifan Tang ◽  
Giovanni De Micheli ◽  
Pierre-Emmanuel Gaillardon
Keyword(s):  
High Performance ◽  
Fpga Architecture

High-Performance FPGA Architecture for Multi-line Beamforming in Ultrasound Applications

2016 ◽  
Author(s):  
Valentino Meacci ◽  
Luca Bassi ◽  
Stefano Ricci ◽  
Enrico Boni ◽  
Piero Tortoli
Keyword(s):  
High Performance ◽  
Fpga Architecture ◽  
Ultrasound Applications

Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power

2011 ◽  
pp. 275-280 ◽  
Author(s):  
Yahya Lakys ◽  
Weisheng Zhao ◽  
Jacques-Olivier Klein ◽  
Claude Chappert
Keyword(s):  
Low Power ◽  
High Performance ◽  
Radiation Hardness ◽  
Look Up Table

scholarly journals Performance Analysis of Enhanced Adaptive Logic Module for High Performance FPGA Architecture

2015 ◽  
Vol 9 (3) ◽  
pp. 215-223
Author(s):  
V.J.K. Kishor Sonti ◽  
Y. Varthamanan ◽  
D. Sivaraman
Keyword(s):  
Performance Analysis ◽  
High Performance ◽  
Adaptive Logic ◽  
Fpga Architecture ◽  
Logic Module

An Efficient FPGA Architecture with High-Performance 2D DWT Processor for Medical Imaging

2016 ◽  
Vol 25 (09) ◽  
pp. 1650110 ◽  
Author(s):  
S. P. Valan Arasu ◽  
S. Baulkani
Keyword(s):  
Medical Imaging ◽  
Low Power ◽  
Image Fusion ◽  
High Performance ◽  
Large Scale ◽  
Medical Images ◽  
Discrete Wavelet ◽  
Significant Information ◽  
Low Area ◽  
Fpga Architecture

Medical image fusion is the process of deriving vital information from multimodality medical images. Some important applications of image fusion are medical imaging, remote control sensing, personal computer vision and robotics. For medical diagnosis, computerized tomography (CT) gives the best information about denser tissue with a lesser amount of distortion and magnetic resonance image (MRI) gives the better information on soft tissue with little higher distortion. The main scheme is to combine CT and MRI images for getting most significant information. The need is to focus on less power consumption and less occupational area in the implementations of the applications involving image fusion using discrete wavelet transform (DWT). To design the DWT processor with low power and area, a low power multiplier and shifter are incorporated in the hardware. This low power DWT improves the spatial resolution of fused image and also preserve the color appearance. Also, the adaptation of the lifting scheme in the 2D DWT process further improves the power reduction. In order to implement this 2D DWT processor in field-programmable gate array (FPGA) architecture as a very large scale integration (VLSI)-based design, the process is simulated with Xilinx 14.1 tools and also using MATLAB. When comparing the performance of this low power DWT and other available methods, this high performance processor has 24%, 54% and 53% of improvements on the parameters like standard deviation (SD), root mean square error (RMSE) and entropy. Thus, we are obtaining a low power, low area and good performance FPGA architecture suited for VLSI, for extracting the needed information from multimodality medical images with image fusion.

A new FPGA architecture for high-performance bit-serial pipeline datapath (abstract)

1998 ◽  
Author(s):  
Tsuyoshi Isshiki ◽  
Takenobu Shimizugashira ◽  
Akihisa Ohta ◽  
Imanuddin Amril ◽  
Hiroaki Kunieda
Keyword(s):  
High Performance ◽  
Fpga Architecture ◽  
Bit Serial

Efficient Utilization of FPGA Using LUT-6 Architecture

2012 ◽  
Vol 241-244 ◽  
pp. 2548-2554
Author(s):  
Razia Zia ◽  
Muzaffar Rao ◽  
Arshad Aziz ◽  
Pervez Akhtar
Keyword(s):  
Embedded Systems ◽  
Market Share ◽  
Boolean Functions ◽  
Field Programmable Gate Array ◽  
Efficient Utilization ◽  
Look Up Table ◽  
Fpga Architecture ◽  
Logic Block ◽  
Field Programmable ◽  
Typical Cell

Field Programmable gate array (FPGA) technology is continuously gaining market share and becoming essential part of the today’s modern embedded systems. The most common FPGA architecture consists of an array of logic blocks called Configurable Logic Block (CLB), I/O pads, and routing channels. In general, a logic block (CLB) consists of logical cells called Slices and other dedicated resources. A typical cell consists of LUTs (Look up table). In modern FPGAs, there are 6-input LUTs instead of 4-input LUTs. In this paper we present the use of 6-input LUT architecture for some Boolean functions (Mux8, Mux16, Mux32, Mux64, SOP64, OR40 and AND40).we show our results in terms of LUTs and Slices and these results are much better as compare to previously reported results that based on 4-input LUTs.

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